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Subject: Re: [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes
To:     linux-arm-kernel@lists.infradead.org
Cc:     Catalin Marinas <catalin.marinas@arm.com>,
        Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
        James Morse <james.morse@arm.com>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        Mark Rutland <mark.rutland@arm.com>,
        kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org
References: <1580215149-21492-1-git-send-email-anshuman.khandual@arm.com>
From:   Anshuman Khandual <anshuman.khandual@arm.com>
Message-ID: <45ce930c-81b3-3161-ced6-34a8c8623ac8@arm.com>
Date:   Fri, 14 Feb 2020 09:53:25 +0530
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On 01/28/2020 06:09 PM, Anshuman Khandual wrote:
> This series is primarily motivated from an adhoc list from Mark Rutland
> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch
> which does macro replacement for various open bits shift encodings in
> various CPU ID registers. This series is based on linux-next 20200124.
> 
> [1] https://patchwork.kernel.org/patch/11287805/
> 
> Is there anything else apart from these changes which can be accommodated
> in this series, please do let me know. Thank you.

Just a gentle ping. Any updates, does this series looks okay ? Is there
anything else related to CPU ID register feature bits, which can be added
up here. FWIW, the series still applies on v5.6-rc1.

> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: James Morse <james.morse@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: kvmarm@lists.cs.columbia.edu
> Cc: linux-kernel@vger.kernel.org
> 
> Anshuman Khandual (6):
>   arm64/cpufeature: Introduce ID_PFR2 CPU register
>   arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register
>   arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register
>   arm64/cpufeature: Define an explicit ftr_id_isar0[] for ID_ISAR0 register
>   arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register
>   arm64/cpufeature: Replace all open bits shift encodings with macros
> 
>  arch/arm64/include/asm/cpu.h    |  1 +
>  arch/arm64/include/asm/sysreg.h | 51 +++++++++++++++++++
>  arch/arm64/kernel/cpufeature.c  | 87 ++++++++++++++++++++++-----------
>  arch/arm64/kernel/cpuinfo.c     |  1 +
>  arch/arm64/kvm/sys_regs.c       |  2 +-
>  5 files changed, 112 insertions(+), 30 deletions(-)
>