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[209.132.180.67]) by mx.google.com with ESMTP id z1si6092052otq.21.2020.02.16.07.33.42; Sun, 16 Feb 2020 07:33:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass (test mode) header.i=@ideasonboard.com header.s=mail header.b="H1nzhNo/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728383AbgBPPdf (ORCPT + 99 others); Sun, 16 Feb 2020 10:33:35 -0500 Received: from perceval.ideasonboard.com ([213.167.242.64]:36838 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726171AbgBPPdf (ORCPT ); Sun, 16 Feb 2020 10:33:35 -0500 Received: from pendragon.ideasonboard.com (81-175-216-236.bb.dnainternet.fi [81.175.216.236]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 2FF742AF; Sun, 16 Feb 2020 16:33:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1581867213; bh=UwjoSQbzdBP1f/alysPDptK1b0h5/YPxmlv920b3QuQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=H1nzhNo/u6R+fv7VOii4nq3lzmTGUwIjEvMzJysT8Z5E4Xd5n/jpEdQwwWs3UdmLS Hag0XOC7vObfBgClP6S/zpdeNutnzui3LnEoqAcGw1cbWcB9GwIQPVs7Z6rkWKCBKn G8vKm6SAoNJ3DBOujoxjgAi7w3aKDVaMyaX0F6xs= Date: Sun, 16 Feb 2020 17:33:15 +0200 From: Laurent Pinchart To: Yuti Amonkar Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, robh+dt@kernel.org, maxime@cerno.tech, airlied@linux.ie, daniel@ffwll.ch, mark.rutland@arm.com, a.hajda@samsung.com, narmstrong@baylibre.com, jonas@kwiboo.se, jernej.skrabec@siol.net, praneeth@ti.com, jsarha@ti.com, tomi.valkeinen@ti.com, mparab@cadence.com, sjakhade@cadence.com Subject: Re: [PATCH v5 1/3] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings. Message-ID: <20200216153315.GD28645@pendragon.ideasonboard.com> References: <1581481604-24499-1-git-send-email-yamonkar@cadence.com> <1581481604-24499-2-git-send-email-yamonkar@cadence.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1581481604-24499-2-git-send-email-yamonkar@cadence.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Yuti, Thank you for the patch. On Wed, Feb 12, 2020 at 05:26:42AM +0100, Yuti Amonkar wrote: > Document the bindings used for the Cadence MHDP DPI/DP bridge in > yaml format. > > Signed-off-by: Yuti Amonkar > Reviewed-by: Rob Herring > --- > .../bindings/display/bridge/cdns,mhdp.yaml | 125 ++++++++++++++++++ > 1 file changed, 125 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > > diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > new file mode 100644 > index 000000000000..e7f84ed1d2da > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > @@ -0,0 +1,125 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Cadence MHDP bridge > + > +maintainers: > + - Swapnil Jakhade > + - Yuti Amonkar > + > +properties: > + compatible: > + enum: > + - cdns,mhdp8546 > + - ti,j721e-mhdp8546 > + > + reg: > + minItems: 1 > + maxItems: 2 > + items: > + - description: > + Register block of mhdptx apb registers upto PHY mapped area(AUX_CONFIG_P). > + The AUX and PMA registers are mapped to associated phy driver. > + - description: > + Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. > + > + reg-names: > + minItems: 1 > + maxItems: 2 > + items: > + - const: mhdptx > + - const: j721e-intg > + > + clocks: > + maxItems: 1 > + description: > + DP bridge clock, it's used by the IP to know how to translate a number of > + clock cycles into a time (which is used to comply with DP standard timings > + and delays). > + > + phys: > + description: Phandle to the DisplyPort phy. > + > + ports: > + type: object > + description: > + Ports as described in Documentation/devicetree/bindings/graph.txt > + > + properties: > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + port@0: > + type: object > + description: > + input port representing the DP bridge input s/input port/Input port/ and s/bridge input/bridge input./ > + > + port@1: > + type: object > + description: > + output port representing the DP bridge output. s/output port/Output port/ > + > + required: > + - port@0 > + - port@1 > + - '#address-cells' > + - '#size-cells' > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: ti,j721e-mhdp8546 > + then: > + properties: > + reg: > + minItems: 2 > + reg-names: > + minItems: 2 > + > +required: > + - compatible > + - clocks > + - reg > + - reg-names > + - phys > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + mhdp: dp-bridge@f0fb000000 { > + compatible = "cdns,mhdp8546"; > + reg = <0xf0 0xfb000000 0x0 0x1000000>; > + reg-names = "mhdptx"; > + clocks = <&mhdp_clock>; > + phys = <&dp_phy>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dp_bridge_input: endpoint { > + remote-endpoint = <&xxx_dpi_output>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dp_bridge_output: endpoint { > + remote-endpoint = <&xxx_dp_connector_input>; > + }; > + }; > + }; > + }; > +... Really good bindings ! With the above comments addressed, as well as he one in reply to Tomi's review, Reviewed-by: Laurent Pinchart -- Regards, Laurent Pinchart