Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
User-Agent: Cyrus-JMAP/3.1.7-802-g7a41c81-fmstable-20200203v1
Mime-Version: 1.0
Message-Id: <3a053c3e-0fec-4ab9-b941-a335524b3303@www.fastmail.com>
In-Reply-To: <CAK8P3a3HsdpLz0aDGem1BrQsNo2mEJOnOsLcKFcLjaERx9dhGg@mail.gmail.com>
References: <1579123790-6894-1-git-send-email-eajames@linux.ibm.com>
 <1579123790-6894-7-git-send-email-eajames@linux.ibm.com>
 <CAK8P3a3HsdpLz0aDGem1BrQsNo2mEJOnOsLcKFcLjaERx9dhGg@mail.gmail.com>
Date:   Mon, 17 Feb 2020 10:26:57 +1030
From:   "Andrew Jeffery" <andrew@aj.id.au>
To:     "Arnd Bergmann" <arnd@arndb.de>,
        "Eddie James" <eajames@linux.ibm.com>
Cc:     linux-aspeed <linux-aspeed@lists.ozlabs.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        DTML <devicetree@vger.kernel.org>,
        "Mark Rutland" <mark.rutland@arm.com>,
        "Jason Cooper" <jason@lakedaemon.net>,
        "Marc Zyngier" <maz@kernel.org>,
        "Rob Herring" <robh+dt@kernel.org>,
        "Thomas Gleixner" <tglx@linutronix.de>,
        "Joel Stanley" <joel@jms.id.au>
Subject: Re: [PATCH v6 06/12] soc: aspeed: Add XDMA Engine Driver
Content-Type: text/plain
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk


On Tue, 11 Feb 2020, at 03:05, Arnd Bergmann wrote:
> On Wed, Jan 15, 2020 at 10:31 PM Eddie James <eajames@linux.ibm.com> wrote:
> >
> > The XDMA engine embedded in the AST2500 and AST2600 SOCs performs PCI
> > DMA operations between the SOC (acting as a BMC) and a host processor
> > in a server.
> >
> > This commit adds a driver to control the XDMA engine and adds functions
> > to initialize the hardware and memory and start DMA operations.
> >
> > Signed-off-by: Eddie James <eajames@linux.ibm.com>
> 
> Hi Eddie,
> 
> I'm missing the bigger picture in the description here, how does this fit into
> the PCIe endpoint framework and the dmaengine subsystem?
> 
> Does the AST2500 show up as a PCIe device in the host, or do you just
> inject DMAs into the host and hope that bypasses the IOMMU?

The host needs to coordinate out-of-band with the BMC to communicate host
addresses to be used. The host should configure the IOMMU as required before
triggering transfers (either from it's own XDMA interface or requesting the BMC
queue the transfer).

Andrew