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Date:   Mon, 17 Feb 2020 17:09:01 +0000
From:   Mark Brown <broonie@kernel.org>
To:     "Ramuthevar, Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@linux.intel.com>
Cc:     linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
        vigneshr@ti.com, mark.rutland@arm.com, robh+dt@kernel.org,
        devicetree@vger.kernel.org, dan.carpenter@oracle.com,
        cheol.yong.kim@intel.com, qi-ming.wu@intel.com
Subject: Re: [PATCH v9 2/2] spi: cadence-quadpsi: Add support for the Cadence
 QSPI controller
Message-ID: <20200217170901.GS9304@sirena.org.uk>
References: <20200214114618.29704-1-vadivel.muruganx.ramuthevar@linux.intel.com>
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On Mon, Feb 17, 2020 at 05:18:10PM +0800, Ramuthevar, Vadivel MuruganX wrote:
> On 14/2/2020 9:09 PM, Mark Brown wrote:

> > This will unconditionally handle the interrupt regardless of if the
> > hardware was actually flagging an interrupt which will break shared
> > interrupts and the fault handling code in genirq.

> Yes, you're correct, it doesn't check unconditionally, will update the
> INT flag in the INT_STATUS register after successful completion of
> read/write operation.
> but in this case it is dedicated to qspi-interrupt,not shared with any other
> HW/SW interrupts.

Currently, on the system you're looking at.  Given that this is already
a widely reused IP there's no guarantee that this will always be the
case, and like I say even without sharing it also defeats the fault
handling code.

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