Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Peng Fan <peng.fan@nxp.com>
To:     "sboyd@kernel.org" <sboyd@kernel.org>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        Abel Vesa <abel.vesa@nxp.com>,
        Leonard Crestez <leonard.crestez@nxp.com>
CC:     "kernel@pengutronix.de" <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>,
        Aisheng Dong <aisheng.dong@nxp.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Anson Huang <anson.huang@nxp.com>,
        Jacky Bai <ping.bai@nxp.com>,
        "l.stach@pengutronix.de" <l.stach@pengutronix.de>
Subject: RE: [PATCH V3 1/4] clk: imx: composite-8m: add
 imx8m_clk_hw_composite_core
Thread-Topic: [PATCH V3 1/4] clk: imx: composite-8m: add
 imx8m_clk_hw_composite_core
Thread-Index: AQHV5wtPHJjqDVyDiUGylTO3QWs3rKgiTgRQ
Date:   Wed, 19 Feb 2020 10:20:17 +0000
Message-ID: <AM0PR04MB4481BEE793A6FEE5588ACEAC88100@AM0PR04MB4481.eurprd04.prod.outlook.com>
References: <1582106022-20926-1-git-send-email-peng.fan@nxp.com>
 <1582106022-20926-2-git-send-email-peng.fan@nxp.com>
In-Reply-To: <1582106022-20926-2-git-send-email-peng.fan@nxp.com>
Accept-Language: en-US
Content-Language: en-US
received-spf: None (protection.outlook.com: nxp.com does not designate
 permitted sender hosts)
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-Network-Message-Id: a9f3b8e8-9f5b-44d8-4507-08d7b5255172
X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Feb 2020 10:20:18.0105
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: /P1I/uUC6bWkCSZ4XEpZthIE3608A+J0Y5yBa9O91wCavvHqr2eJBeDf4/sgmPxhrFzPc36Ix4a8sFIZ/AWmbA==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6884
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

> Subject: [PATCH V3 1/4] clk: imx: composite-8m: add
> imx8m_clk_hw_composite_core

Sorry, some patches are wrongly sent out, please ignore this thread.
I'll use PATCH RESEND to resend and drop unneed patches.

Thanks,
Peng.

>=20
> From: Peng Fan <peng.fan@nxp.com>
>=20
> There are several clock slices, current composite code only support bus/i=
p
> clock slices, it could not support core slice.
>=20
> So introduce a new API imx8m_clk_hw_composite_core to support core slice.
> To core slice, post divider with 3 bits width and no pre divider. Other f=
ields are
> same as bus/ip slices.
>=20
> Add a flag IMX_COMPOSITE_CORE for the usecase.
>=20
> Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/imx/clk-composite-8m.c | 18 ++++++++++++++----
>  drivers/clk/imx/clk.h              | 13 +++++++++++--
>  2 files changed, 25 insertions(+), 6 deletions(-)
>=20
> diff --git a/drivers/clk/imx/clk-composite-8m.c
> b/drivers/clk/imx/clk-composite-8m.c
> index e0f25983e80f..4174506e8bdd 100644
> --- a/drivers/clk/imx/clk-composite-8m.c
> +++ b/drivers/clk/imx/clk-composite-8m.c
> @@ -15,6 +15,7 @@
>  #define PCG_PREDIV_MAX		8
>=20
>  #define PCG_DIV_SHIFT		0
> +#define PCG_CORE_DIV_WIDTH	3
>  #define PCG_DIV_WIDTH		6
>  #define PCG_DIV_MAX		64
>=20
> @@ -126,6 +127,7 @@ static const struct clk_ops
> imx8m_clk_composite_divider_ops =3D {  struct clk_hw
> *imx8m_clk_hw_composite_flags(const char *name,
>  					const char * const *parent_names,
>  					int num_parents, void __iomem *reg,
> +					u32 composite_flags,
>  					unsigned long flags)
>  {
>  	struct clk_hw *hw =3D ERR_PTR(-ENOMEM), *mux_hw; @@ -133,6 +135,7
> @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>  	struct clk_divider *div =3D NULL;
>  	struct clk_gate *gate =3D NULL;
>  	struct clk_mux *mux =3D NULL;
> +	const struct clk_ops *divider_ops;
>=20
>  	mux =3D kzalloc(sizeof(*mux), GFP_KERNEL);
>  	if (!mux)
> @@ -149,8 +152,16 @@ struct clk_hw
> *imx8m_clk_hw_composite_flags(const char *name,
>=20
>  	div_hw =3D &div->hw;
>  	div->reg =3D reg;
> -	div->shift =3D PCG_PREDIV_SHIFT;
> -	div->width =3D PCG_PREDIV_WIDTH;
> +	if (composite_flags & IMX_COMPOSITE_CORE) {
> +		div->shift =3D PCG_DIV_SHIFT;
> +		div->width =3D PCG_CORE_DIV_WIDTH;
> +		divider_ops =3D &clk_divider_ops;
> +	} else {
> +		div->shift =3D PCG_PREDIV_SHIFT;
> +		div->width =3D PCG_PREDIV_WIDTH;
> +		divider_ops =3D &imx8m_clk_composite_divider_ops;
> +	}
> +
>  	div->lock =3D &imx_ccm_lock;
>  	div->flags =3D CLK_DIVIDER_ROUND_CLOSEST;
>=20
> @@ -164,8 +175,7 @@ struct clk_hw
> *imx8m_clk_hw_composite_flags(const char *name,
>=20
>  	hw =3D clk_hw_register_composite(NULL, name, parent_names,
> num_parents,
>  			mux_hw, &clk_mux_ops, div_hw,
> -			&imx8m_clk_composite_divider_ops,
> -			gate_hw, &clk_gate_ops, flags);
> +			divider_ops, gate_hw, &clk_gate_ops, flags);
>  	if (IS_ERR(hw))
>  		goto fail;
>=20
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index
> b05213b91dcf..f074dd8ec42e 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -477,20 +477,29 @@ struct clk_hw *imx_clk_hw_cpu(const char *name,
> const char *parent_name,
>  		struct clk *div, struct clk *mux, struct clk *pll,
>  		struct clk *step);
>=20
> +#define IMX_COMPOSITE_CORE	BIT(0)
> +
>  struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>  					    const char * const *parent_names,
>  					    int num_parents,
>  					    void __iomem *reg,
> +					    u32 composite_flags,
>  					    unsigned long flags);
>=20
> +#define imx8m_clk_hw_composite_core(name, parent_names, reg)	\
> +	imx8m_clk_hw_composite_flags(name, parent_names, \
> +			ARRAY_SIZE(parent_names), reg, \
> +			IMX_COMPOSITE_CORE, \
> +			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
> +
>  #define imx8m_clk_composite_flags(name, parent_names, num_parents,
> reg, \
>  				  flags) \
>  	to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
> -				num_parents, reg, flags))
> +				num_parents, reg, 0, flags))
>=20
>  #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \
>  	imx8m_clk_hw_composite_flags(name, parent_names, \
> -		ARRAY_SIZE(parent_names), reg, \
> +		ARRAY_SIZE(parent_names), reg, 0, \
>  		flags | CLK_SET_RATE_NO_REPARENT |
> CLK_OPS_PARENT_ENABLE)
>=20
>  #define __imx8m_clk_composite(name, parent_names, reg, flags) \
> --
> 2.16.4