Received: by 2002:a25:1506:0:0:0:0:0 with SMTP id 6csp485675ybv; Wed, 19 Feb 2020 03:34:21 -0800 (PST) X-Google-Smtp-Source: APXvYqzWERlmpYDu/PzLg2fxsyITWgoAAV+3kBhAQ/t2AOUtNvD/SFVtrUatVyBe0vPpDObPGiPd X-Received: by 2002:aca:af50:: with SMTP id y77mr4413130oie.8.1582112061074; Wed, 19 Feb 2020 03:34:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1582112061; cv=none; d=google.com; s=arc-20160816; b=jTOYyBWmVTHPw5shByfNtg7+6k6zS/QicoyUsmHR8+ukIOdSTgHhRzT1YFzvQXf/mm 5Oy8RpMZXaQ+5Y1z8jdYPpkL/lxhq4Q0ZvDAZqMACB+nTJOeq+O25bLZFiKRE5RB/ySN WZ3mzmB8+Rw99JyGcoFaE5lwgROdW7o+2yFz/x1C5bBEWBSoLu1eHT8gAcLD5ukMS79n VCrC5R3uKzwcAtEtCqsln716wNtlrIfCovr22emdn2eyJyfNQhx+GpK3Jlpo/B7zdhzn YBxYUtJXcY4a3R8Aw3cNXqXzZEg08xdppKdjiSj31dXWhX4ekTYtapVhBxUZVNAdb0fm Rq3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:references:cc:to:from:subject:dkim-signature; bh=7rGcCAIJ1owBgJnQqs9fghPribnH6MLQt7KvBtj4rlU=; b=mY07lFEwZgfcvErtx2niXGuzGUmH54eed+uaN8/bRSzVE3q26GX7FeHEB6wheqYn+d D2Jx3aPwYCZj9Ky4dgM/lBWu99YCLpy3aGb3GQdS44y9x1crOzmY3XifQ4QGD5vAwTqH mE7irsd41q1IXRl1f17ZAHzHVi/9olNnLcN2NB+cCy6mkE2bblsKHy7SOSfXFh0/uNDP je0xf27Spd6o/O4FJSVwARey1L8q2AUw/MKkShuEO+O61pTdYLHn4L6hIVWiGdDpUhY3 DI1gyw+8rKiGUbLKuPp40dvORToQhS2OZMjbq0vtD2709NvvuKssrBxi+/2iXyoWSLCn gTGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=beCCWjxb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=st.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f190si9905753oig.229.2020.02.19.03.34.09; Wed, 19 Feb 2020 03:34:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=beCCWjxb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=st.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726856AbgBSLeB (ORCPT + 99 others); Wed, 19 Feb 2020 06:34:01 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:23656 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726270AbgBSLeB (ORCPT ); Wed, 19 Feb 2020 06:34:01 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 01JBO4UN023951; Wed, 19 Feb 2020 12:33:37 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=subject : from : to : cc : references : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=STMicroelectronics; bh=7rGcCAIJ1owBgJnQqs9fghPribnH6MLQt7KvBtj4rlU=; b=beCCWjxbEgVdPTO/oTEiGoMJE2z1U7oqaAWze4ZQJ3BM6EXShjbWtD8h1a6ACcpNmJl9 8hBbCDobb3eS8gKl2gD254uN1rDjiWOy7ZBh8V9vyzEXPlptxniqr1V3vAhJ6OP96y7B Yh3/trpblCtyDZiwcyxoo73F8pUv6YWIRPv7rN+hQYekkGgGJV7XYPxf8SpcQlr9C3Iy yHRue8YPJR1mS4nE2C7F+1htjGZhL4g6oJWVU5LcZhQAJSWYGCpLsoNi/T8mZqGPmavQ LaabaXCIyf+LJj+Othr1isoNkOiJxoG1grSgZ7qJGDvnoqyarPL1Yn4DZ8usjLAoOIAz PQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2y8ub5jrch-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Feb 2020 12:33:37 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9B0E4100034; Wed, 19 Feb 2020 12:33:32 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 88A4D2B2DE2; Wed, 19 Feb 2020 12:33:32 +0100 (CET) Received: from lmecxl0912.lme.st.com (10.75.127.46) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 19 Feb 2020 12:33:31 +0100 Subject: Re: [PATCH v2 1/2] irqchip/stm32: Add irq retrigger support From: Alexandre Torgue To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Linus Walleij CC: , , , References: <20200218131218.10789-1-alexandre.torgue@st.com> <20200218131218.10789-2-alexandre.torgue@st.com> Message-ID: <16d27f75-8157-7a92-ae61-b5b3ab05bdd9@st.com> Date: Wed, 19 Feb 2020 12:33:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200218131218.10789-2-alexandre.torgue@st.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG7NODE1.st.com (10.75.127.19) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.572 definitions=2020-02-19_03:2020-02-19,2020-02-19 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix Marc email address On 2/18/20 2:12 PM, Alexandre Torgue wrote: > This commit introduces retrigger support for stm32_ext_h chip. > It consists to rise the GIC interrupt mapped to an EXTI line. > > Signed-off-by: Alexandre Torgue > > diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c > index e00f2fa27f00..c971d115edb4 100644 > --- a/drivers/irqchip/irq-stm32-exti.c > +++ b/drivers/irqchip/irq-stm32-exti.c > @@ -604,12 +604,24 @@ static void stm32_exti_h_syscore_deinit(void) > unregister_syscore_ops(&stm32_exti_h_syscore_ops); > } > > +static int stm32_exti_h_retrigger(struct irq_data *d) > +{ > + struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); > + const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; > + void __iomem *base = chip_data->host_data->base; > + u32 mask = BIT(d->hwirq % IRQS_PER_BANK); > + > + writel_relaxed(mask, base + stm32_bank->swier_ofst); > + > + return irq_chip_retrigger_hierarchy(d); > +} > + > static struct irq_chip stm32_exti_h_chip = { > .name = "stm32-exti-h", > .irq_eoi = stm32_exti_h_eoi, > .irq_mask = stm32_exti_h_mask, > .irq_unmask = stm32_exti_h_unmask, > - .irq_retrigger = irq_chip_retrigger_hierarchy, > + .irq_retrigger = stm32_exti_h_retrigger, > .irq_set_type = stm32_exti_h_set_type, > .irq_set_wake = stm32_exti_h_set_wake, > .flags = IRQCHIP_MASK_ON_SUSPEND, >