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[209.132.180.67]) by mx.google.com with ESMTP id f14si1099753oto.46.2020.02.19.06.33.17; Wed, 19 Feb 2020 06:33:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=HWt1AHlC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=st.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727951AbgBSOcw (ORCPT + 99 others); Wed, 19 Feb 2020 09:32:52 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:25686 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727434AbgBSOcw (ORCPT ); Wed, 19 Feb 2020 09:32:52 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 01JES7bO001942; Wed, 19 Feb 2020 15:32:36 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=0aye/Mln2NvmkOZxtnRrVlrGHhkkcd2paFim0fiOSGY=; b=HWt1AHlCUmUJYwbzGfJtfqqd46XRz+v4oTGiQi0txpDP5ncTsHUb17py+WpxIufYVcLy mq5AA/nHnR4yNjcPN/VgfEajmPymIibr7FEaz3o8GbQ5n9T1sMzIbG3wS+OTRXtMZsGq /2S1ZochigIjOUO0VK7SoIwVEgB4n7RolzMwS5QzwFbS59aWjmxQTDsc3oj1rPEnhehH bJZRuGHqer2woWyJN3JFkklHVCQ4G3MrqC6OGlvP5PYJU/DqVv0hZsorU27VgSOKSs01 NBiErFIYaNJUXGxhn+UZsVhjgZN0yzq5E2ahZrwIjc5omB9fmj6g9ssh+wJstDWrPJir fw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2y8ub5kjc4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Feb 2020 15:32:36 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AFB1210003D; Wed, 19 Feb 2020 15:32:31 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A59682BEC59; Wed, 19 Feb 2020 15:32:31 +0100 (CET) Received: from localhost (10.75.127.47) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 19 Feb 2020 15:32:31 +0100 From: Alexandre Torgue To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Linus Walleij CC: , , , , Subject: [PATCH v3 1/2] irqchip/stm32: Add irq retrigger support Date: Wed, 19 Feb 2020 15:32:28 +0100 Message-ID: <20200219143229.18084-2-alexandre.torgue@st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200219143229.18084-1-alexandre.torgue@st.com> References: <20200219143229.18084-1-alexandre.torgue@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG7NODE3.st.com (10.75.127.21) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.572 definitions=2020-02-19_03:2020-02-19,2020-02-19 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This commit introduces retrigger support for stm32_ext_h chip. It consists to rise the GIC interrupt mapped to an EXTI line. Signed-off-by: Alexandre Torgue Tested-by: Marek Vasut diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index e00f2fa27f00..faa8482c8246 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -604,12 +604,24 @@ static void stm32_exti_h_syscore_deinit(void) unregister_syscore_ops(&stm32_exti_h_syscore_ops); } +static int stm32_exti_h_retrigger(struct irq_data *d) +{ + struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); + const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; + void __iomem *base = chip_data->host_data->base; + u32 mask = BIT(d->hwirq % IRQS_PER_BANK); + + writel_relaxed(mask, base + stm32_bank->swier_ofst); + + return 0; +} + static struct irq_chip stm32_exti_h_chip = { .name = "stm32-exti-h", .irq_eoi = stm32_exti_h_eoi, .irq_mask = stm32_exti_h_mask, .irq_unmask = stm32_exti_h_unmask, - .irq_retrigger = irq_chip_retrigger_hierarchy, + .irq_retrigger = stm32_exti_h_retrigger, .irq_set_type = stm32_exti_h_set_type, .irq_set_wake = stm32_exti_h_set_wake, .flags = IRQCHIP_MASK_ON_SUSPEND, -- 2.17.1