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[209.132.180.67]) by mx.google.com with ESMTP id e1si934524otr.8.2020.02.19.18.21.51; Wed, 19 Feb 2020 18:22:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=IJZnCzHl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727877AbgBTCVP (ORCPT + 99 others); Wed, 19 Feb 2020 21:21:15 -0500 Received: from mail-pl1-f194.google.com ([209.85.214.194]:42548 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727291AbgBTCVO (ORCPT ); Wed, 19 Feb 2020 21:21:14 -0500 Received: by mail-pl1-f194.google.com with SMTP id e8so907998plt.9 for ; Wed, 19 Feb 2020 18:21:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:content-transfer-encoding:in-reply-to:references :subject:from:cc:to:date:message-id:user-agent; bh=YAR5AKH97O4wD1WPqWhh58Z+vTDyTGU+wowRu7veeWo=; b=IJZnCzHlX08ZA7i7SWUg3SVtMUVih+MtyIhM06LeI0WUnLEa/A/npW9fObuTqHp5bR ng5U6jk3rSrmAJ5psu8/fWOitlD/WVffCzwla/GH8evP5zKSx+xXS6sG+O34VufGl4ih fmsg6Os6z9BY6etm4kkLqKNOE9U5+BSnxFpT4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:content-transfer-encoding :in-reply-to:references:subject:from:cc:to:date:message-id :user-agent; bh=YAR5AKH97O4wD1WPqWhh58Z+vTDyTGU+wowRu7veeWo=; b=BuPX6X/SY7bFCmSHZ3hx6IKf9rGGrtsAKxC5ZstMXKmh3GRyjf0tmU9FDa+mC6w991 Mn1piFtCVcTl+pZy2VMhtdDiOiB3R9LZrjEC44y+yNFNhrfJFmQ6oonCd2FlCudApJD/ kIhEJ5xClnR6tWO3yhH4tH0ZsCVtYcLm7uDNXVLVtvHfCklArHY/Ns3A212oJ69XEGA/ m5I1lCa0aF10vOShlBjk8bdp/lkN0NsyKDaql0AUAyrDTDzuMCMTbXM4UYoHwfEY3e7K DPknHWFSwoz6nBKslZIJYjaT9BKJ0G1ctmyT2lAV24xHd2k9Q9ZZgLp+Khfd9rhnSkgN ox3A== X-Gm-Message-State: APjAAAX1nCh1DS9V1n4EazwMmEkIgs4OFHgMVp4lhRcBsIN2ykzKVEzv Z454jfv3gOcdAF5Sh6pUhEtSDQt2org= X-Received: by 2002:a17:902:502:: with SMTP id 2mr28499313plf.151.1582165273803; Wed, 19 Feb 2020 18:21:13 -0800 (PST) Received: from chromium.org ([2620:15c:202:1:fa53:7765:582b:82b9]) by smtp.gmail.com with ESMTPSA id h185sm956137pfg.135.2020.02.19.18.21.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Feb 2020 18:21:13 -0800 (PST) Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <1581944408-7656-2-git-send-email-mkshah@codeaurora.org> References: <1581944408-7656-1-git-send-email-mkshah@codeaurora.org> <1581944408-7656-2-git-send-email-mkshah@codeaurora.org> Subject: Re: [RFC 1/2] irqchip: qcom: pdc: Introduce irq_set_wake call From: Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, agross@kernel.org, linus.walleij@linaro.org, tglx@linutronix.de, dianders@chromium.org, rnayak@codeaurora.org, ilina@codeaurora.org, lsrao@codeaurora.org, Maulik Shah To: Maulik Shah , bjorn.andersson@linaro.org, evgreen@chromium.org, mka@chromium.org Date: Wed, 19 Feb 2020 18:21:12 -0800 Message-ID: <158216527227.184098.17500969657143611632@swboyd.mtv.corp.google.com> User-Agent: alot/0.9 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The subject should be something different. "Fix irq wake when irqs are disabled"? Quoting Maulik Shah (2020-02-17 05:00:07) > Change the way interrupts get enabled at wakeup capable PDC irq chip. > Introduce irq_set_wake call which lets interrupts enabled at PDC with > enable_irq_wake and disabled with disable_irq_wake. >=20 > Remove irq_disable and irq_enable calls which now will default to irq_mask > and irq_unmask. >=20 This commit text is pretty useless. It says what is happening in the patch but doesn't explain why anything is changing or why anyone should care. How are wakeups supposed to work when the CPU cluster power is disabled in low power CPU idle modes? Presumably the parent irq controller is powered off (in this case it's an ARM GIC) and we would need to have the interrupt be "enabled" or "unmasked" at the PDC for the irq to wakeup the cluster. We shouldn't need to enable irq wake on any irq for the CPU to get that interrupt in deep CPU idle states.