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Subject: Re: Questions about logic_pio
To:     Jiaxun Yang <jiaxun.yang@flygoat.com>,
        yuanzhichang <yuanzhichang@hisilicon.com>,
        <john.garry@huawei.com>,
        gabrielepaoloni <gabriele.paoloni@huawei.com>,
        bhelgaas <bhelgaas@google.com>,
        andyshevchenko <andy.shevchenko@gmail.com>
References: <1705dbe62ce.10ae800394772.9222265269135747883@flygoat.com>
CC:     linux-kernel <linux-kernel@vger.kernel.org>
From:   Wei Xu <xuwei5@hisilicon.com>
Message-ID: <5E4E55F7.70800@hisilicon.com>
Date:   Thu, 20 Feb 2020 17:48:39 +0800
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Hi Jiaxun,

On 2020/2/19 21:58, Jiaxun Yang wrote:
> Hi there,
> 
> Logic PIO gives us a way to make indirect PIO access, however,
> the way it handles direct (MMIO) I/O access confused me.
> 
> I was trying to create a PCI controller Driver and noticed that I/O range parsed
> from DeviceTree will be added to the Logic PIO range by logic_pio_register_range. 
> And than PCI subsystem will use the ioport obtained from `logic_pio_trans_cpuaddr`
> to allocate resources for the host bridge. In my case, the range added to the logic pio
>  was set as hw_start 0x4000, size 0x4000. Later, `logic_pio_trans_cpuaddr` called
> by `pci_address_to_pio` gives a ioport of 0x0, which is totally wrong.
> 
> After dig into logic pio logic, I found that logic pio is trying to "allocate" an io_start
> for MMIO ranges, the allocation starts from 0x0. And later the io_start is used to calculate
> cpu_address.  In my opinion, for direct MMIO access, logic_pio address should always
> equal to hw address, because there is no way to translate address from logic pio address
> to actual hw address in {in,out}{b,sb,w,sb,l,sl} operations.
> 
> How this mechanism intends to work? What is the reason that we are trying to
> allocate a io_start for MMIO rather than take their hw_start ioport directly?
> 
> Thanks. 

Corrected John's mail address.
Maybe he can help.

Best Regards,
Wei

> 
> --
> Jiaxun Yang
> 
> 
> 
> .
>