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Date:   Thu, 20 Feb 2020 15:06:00 +0000
From:   Marc Zyngier <maz@kernel.org>
To:     minyard@acm.org
Cc:     Will Deacon <will@kernel.org>,
        Catalin Marinas <catalin.marinas@arm.com>,
        linux-arm-kernel@lists.infradead.org,
        Corey Minyard <cminyard@mvista.com>,
        linux-kernel@vger.kernel.org, Corey Minyard <tcminyard@gmail.com>
Subject: Re: [PATCH v2] arm64:kgdb: Fix kernel single-stepping
In-Reply-To: <20200220145048.GH3704@minyard.net>
References: <20200219152403.3495-1-minyard@acm.org>
 <1416dca51b52dff349923184f41d48e8@kernel.org>
 <20200220145048.GH3704@minyard.net>
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On 2020-02-20 14:50, Corey Minyard wrote:
> On Thu, Feb 20, 2020 at 02:21:36PM +0000, Marc Zyngier wrote:
>> On 2020-02-19 15:24, minyard@acm.org wrote:
>> > From: Corey Minyard <cminyard@mvista.com>
>> 
>> [...]
>> 
>> > After studying the EL0 handling for this, I realized an issue with using
>> > MDSCR to check if single step is enabled: it can be expensive on a VM.
>> > So check the task flag first to see if single step is enabled.  Then
>> > check MDSCR if the task flag is set.
>> 
>> Very tangential remark: I'd really like people *not* to try and 
>> optimize
>> Linux based on the behaviour of a hypervisor. In general, reading a
>> system register is fast, and the fact that it traps on a given 
>> hypervisor
>> at some point may not be true in the future, nor be a valid assumption
>> across hypervisors.
> 
> Normally I would agree, but I based this upon git commit
> https://github.com/torvalds/linux/commit/2a2830703a2371b47f7b50b1d35cb15dc0e2b717
> which seemed to say that it was a significant enough factor to do in 
> the
> EL0 case.

And that's a blast from a distant past. Hypervisors have changed 
drastically
over these 6 years, and I'm still sitting on a bunch of patches that 
*could*
change the way MDSCR_EL1 is handled.

         M.
-- 
Jazz is not dead. It just smells funny...