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Date:   Thu, 20 Feb 2020 11:49:43 -0500
From:   Sasha Levin <sashal@kernel.org>
To:     Suman Anna <s-anna@ti.com>
Cc:     linux-kernel@vger.kernel.org, stable@vger.kernel.org,
        Tony Lindgren <tony@atomide.com>, linux-omap@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH AUTOSEL 5.5 219/542] ARM: OMAP2+: use separate IOMMU
 pdata to fix DRA7 IPU1 boot
Message-ID: <20200220164943.GF1734@sasha-vm>
References: <20200214154854.6746-1-sashal@kernel.org>
 <20200214154854.6746-219-sashal@kernel.org>
 <a7666322-f931-63f1-a4c5-d44c2ba4ed0c@ti.com>
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On Fri, Feb 14, 2020 at 12:34:58PM -0600, Suman Anna wrote:
>Hi Sasha,
>
>On 2/14/20 9:43 AM, Sasha Levin wrote:
>> From: Suman Anna <s-anna@ti.com>
>>
>> [ Upstream commit 4601832f40501efc3c2fd264a5a69bd1ac17d520 ]
>>
>> The IPU1 MMU has been using common IOMMU pdata quirks defined and
>> used by all IPU IOMMU devices on OMAP4 and beyond. Separate out the
>> pdata for IPU1 MMU with the additional .set_pwrdm_constraint ops
>> plugged in, so that the IPU1 power domain can be restricted to ON
>> state during the boot and active period of the IPU1 remote processor.
>> This eliminates the pre-conditions for the IPU1 boot issue as
>> described in commit afe518400bdb ("iommu/omap: fix boot issue on
>> remoteprocs with AMMU/Unicache").
>>
>> NOTE:
>> 1. RET is not a valid target power domain state on DRA7 platforms,
>>    and IPU power domain is normally programmed for OFF. The IPU1
>>    still fails to boot though, and an unclearable l3_noc error is
>>    thrown currently on 4.14 kernel without this fix. This behavior
>>    is slightly different from previous 4.9 LTS kernel.
>> 2. The fix is currently applied only to IPU1 on DRA7xx SoC, as the
>>    other affected processors on OMAP4/OMAP5/DRA7 are in domains
>>    that are not entering RET. IPU2 on DRA7 is in CORE power domain
>>    which is only programmed for ON power state. The fix can be easily
>>    scaled if these domains do hit RET in the future.
>> 3. The issue was not seen on current DRA7 platforms if any of the
>>    DSP remote processors were booted and using one of the GPTimers
>>    5, 6, 7 or 8 on previous 4.9 LTS kernel. This was due to the
>>    errata fix for i874 implemented in commit 1cbabcb9807e ("ARM:
>>    DRA7: clockdomain: Implement timer workaround for errata i874")
>>    which keeps the IPU1 power domain from entering RET when the
>>    timers are active. But the timer workaround did not make any
>>    difference on 4.14 kernel, and an l3_noc error was seen still
>>    without this fix.
>>
>> Signed-off-by: Suman Anna <s-anna@ti.com>
>> Signed-off-by: Tony Lindgren <tony@atomide.com>
>> Signed-off-by: Sasha Levin <sashal@kernel.org>
>
>And drop this one as well, since mainline doesn't yet boot
>the processors, so this is not needed for stable queue.

Now dropped, thank you.

-- 
Thanks,
Sasha