Received: by 2002:a25:1506:0:0:0:0:0 with SMTP id 6csp1016851ybv; Thu, 20 Feb 2020 11:30:00 -0800 (PST) X-Google-Smtp-Source: APXvYqzKESv4JKmAIxHqsUrGFcDaC4IRZPdYlTppbjuPsm7lD76dQVwOdOB7ePYdlUc5MAJuRN7Y X-Received: by 2002:aca:cf94:: with SMTP id f142mr3194797oig.31.1582227000030; Thu, 20 Feb 2020 11:30:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1582227000; cv=none; d=google.com; s=arc-20160816; b=urSIGXjy4ufrEmQRSg/99KPLFMJKNqU9+jcIDA4BO29U+3NAdeyS6RLdJsgrryUJ0g Z4sASpgIWGP6X4irNJC18pWJVwM2hvJWTRn449Tr8YTNLY4uFRkb2nm2O8M6GGFUTRJi kzKYHK8UKzobR/boKLsXdoLtD50ybg0I1SApJf/2g3pNMUSK4Qi0EtJtl4Q4T/Gf35bA yuCXny+SGhuPkkPqYlpBnzcP83fccYz3naiJZrISp5AJVwJUreraavS0u+IPx3R98Hto ttUeXeGjGuSdWi7AgKGUC7zitfL4b3EK0sigz+FkcEO/OUippeftpyMxyquy1hM8AHng 4Lbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=4KCbuBfxCPj/h+c91f5qB8eGv8IVA+f2xuEVLx6H5NI=; b=STpxdF/6MQ3NXE/Pd7/nIJPaiYLoUPV1TW2wlsqbr70u2HyJp2VVNlyGdcM/KFzEgi d/ZL0jRVsX/fAVt2BDQsQGrSX4YtFDUgtX6H24hcvTWbjpdIvyYVZ6q8sHNt7uVx9LQ/ wYziLJsTMeEGuREBGqtQmokMS9DzCoXI3UUAww3xTIfoJxxtrAjr7Ya3qmMxjkRzG4cl p8SplgdaZPzXMBYH1hnkps4z541/fAATdWZuY2ThiJULrDEc215gH219pKceG9XL4R62 egJhVWrYBRRNSxPhZQiJehmwnCoj6lPFJXglYgPuD2EYN5lnEMZ4HaPXRZfVSvI8VsAk NlSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e1si202183otr.8.2020.02.20.11.29.48; Thu, 20 Feb 2020 11:30:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728846AbgBTT3i (ORCPT + 99 others); Thu, 20 Feb 2020 14:29:38 -0500 Received: from mga01.intel.com ([192.55.52.88]:16662 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728248AbgBTT3h (ORCPT ); Thu, 20 Feb 2020 14:29:37 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Feb 2020 11:29:37 -0800 X-IronPort-AV: E=Sophos;i="5.70,465,1574150400"; d="scan'208";a="228993647" Received: from ykim6-mobl1.amr.corp.intel.com (HELO arch-ashland-svkelley.intel.com) ([10.254.188.97]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 20 Feb 2020 11:29:36 -0800 From: Sean V Kelley To: tglx@linutronix.de, bhelgaas@google.com, corbet@lwn.net, mingo@redhat.com, bp@alien8.de Cc: x86@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kar.hin.ong@ni.com, sassmann@kpanic.de, Sean V Kelley Subject: [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets Date: Thu, 20 Feb 2020 11:29:28 -0800 Message-Id: <20200220192930.64820-1-sean.v.kelley@linux.intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changes since v1 [1]: - Correct Documentation section title for 6300ESB chipset. (Jonathan Derrick) - Use consistent abbreviations in comments for IO-APIC and Core IO. (Andy Shevchenko) - Retained Reviewed-by tag due to no technical changes. [1]: https://lore.kernel.org/lkml/20200214213313.66622-1-sean.v.kelley@linux.intel.com/ Bjorn, I'm open for it to go to stable as well. -- When IRQ lines on secondary or higher IO-APICs are masked (e.g., Real-Time threaded interrupts), many chipsets redirect IRQs on this line to the legacy PCH and in turn the base IO-APIC in the system. The unhandled interrupts on the base IO-APIC will be identified by the Linux kernel as Spurious Interrupts and can lead to disabled IRQ lines. Disabling this legacy PCI interrupt routing is chipset-specific and varies in mechanism between chipset vendors and across generations. In some cases the mechanism is exposed to BIOS but not all BIOS vendors chose to pick it up. With the increasing usage of RT as it marches towards mainline, additional issues have been raised with more recent Xeon chipsets. This patchset disables the boot interrupt on these Xeon chipsets where this is possible with an additional mechanism. In addition, this patchset includes documentation covering the background of this quirk. Sean V Kelley (2): pci: Add boot interrupt quirk mechanism for Xeon chipsets Documentation:PCI: Add background on Boot Interrupts Documentation/PCI/boot-interrupts.rst | 153 ++++++++++++++++++++++++++ Documentation/PCI/index.rst | 1 + drivers/pci/quirks.c | 80 ++++++++++++-- 3 files changed, 227 insertions(+), 7 deletions(-) create mode 100644 Documentation/PCI/boot-interrupts.rst -- 2.25.1