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[209.132.180.67]) by mx.google.com with ESMTP id k8si787850otp.69.2020.02.20.19.08.48; Thu, 20 Feb 2020 19:09:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=OGCa9t1q; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729546AbgBUDIj (ORCPT + 99 others); Thu, 20 Feb 2020 22:08:39 -0500 Received: from conuserg-10.nifty.com ([210.131.2.77]:53866 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729412AbgBUDIi (ORCPT ); Thu, 20 Feb 2020 22:08:38 -0500 Received: from localhost.localdomain (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id 01L37I3Y000971; Fri, 21 Feb 2020 12:07:18 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com 01L37I3Y000971 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1582254439; bh=Ylca/nhJZzm9YX87gCCuGP3STinxK4tvxFG6fALXuaw=; h=From:To:Cc:Subject:Date:From; b=OGCa9t1qm11PkrlL3Oh1a/KETNzQrTocCkRiu3MXaW+RSjwh7Jb+8Urqw8YDVCgXa naewYXcv8TETu6kpdbK3AxU0pco2oQqA6GEa+zROhhkiB94L0qBJwooACn3ry51w+t OTaRQUrvQYZDiUS9deUdL36G8wetFgpQDjUd95mIivq8HOCtSB9Ta3hJYvVtbXJPss T4kyHElgkD97kHx0LoSnfENYUvbXps7Wu3LL4Y9/Ip617elgnjcWJiKvR9WMQtVu3t 3N7uJR2xYqWZgeNvMulLhYla9ueLeiZ6CgiHmvEy/EYHqRaMauvqd/9pfZqH71lX50 RDVK8n3v4maSg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: devicetree@vger.kernel.org, Rob Herring Cc: Frank Rowand , Masahiro Yamada , Jason Cooper , Marc Zyngier , Mark Rutland , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] dt-bindings: interrupt-controller: Convert UniPhier AIDET to json-schema Date: Fri, 21 Feb 2020 12:07:13 +0900 Message-Id: <20200221030713.438-1-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.17.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the UniPhier AIDET (ARM Interrupt Detector) binding to DT schema format. Signed-off-by: Masahiro Yamada --- Some qeustions: I was wondering when 'additionalProperties: false' should be added. If I add it to a bus controller device (e.g. I2C), I see some schema warnings because various sub-nodes are added depending on which device you connect. On the other hand, the interrupt controller like this does not have a subnode. So, probably this is the case where we can add 'additionalProperties: false'. Is this correct? One more thing. There are multiple ways to do a similar thing: compatible: enum: - socionext,uniphier-ld4-aidet - socionext,uniphier-pro4-aidet ... vs compatible: oneOf: - const: socionext,uniphier-ld4-aidet - const: socionext,uniphier-pro4-aidet ... I adopted the former because I can save 'const'. If there is a preferred way, I will follow it. .../socionext,uniphier-aidet.txt | 32 ---------- .../socionext,uniphier-aidet.yaml | 61 +++++++++++++++++++ 2 files changed, 61 insertions(+), 32 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt deleted file mode 100644 index 48e71d3ac2ad..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt +++ /dev/null @@ -1,32 +0,0 @@ -UniPhier AIDET - -UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic -Interrupt Controller). GIC itself can handle only high level and rising edge -interrupts. The AIDET provides logic inverter to support low level and falling -edge interrupts. - -Required properties: -- compatible: Should be one of the following: - "socionext,uniphier-ld4-aidet" - for LD4 SoC - "socionext,uniphier-pro4-aidet" - for Pro4 SoC - "socionext,uniphier-sld8-aidet" - for sLD8 SoC - "socionext,uniphier-pro5-aidet" - for Pro5 SoC - "socionext,uniphier-pxs2-aidet" - for PXs2/LD6b SoC - "socionext,uniphier-ld11-aidet" - for LD11 SoC - "socionext,uniphier-ld20-aidet" - for LD20 SoC - "socionext,uniphier-pxs3-aidet" - for PXs3 SoC -- reg: Specifies offset and length of the register set for the device. -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an interrupt - source. The value should be 2. The first cell defines the interrupt number - (corresponds to the SPI interrupt number of GIC). The second cell specifies - the trigger type as defined in interrupts.txt in this directory. - -Example: - - aidet: aidet@5fc20000 { - compatible = "socionext,uniphier-pro4-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml new file mode 100644 index 000000000000..e61748df2e2c --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/socionext,uniphier-aidet.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier AIDET + +description: | + UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC + (Generic Interrupt Controller). GIC itself can handle only high level and + rising edge interrupts. The AIDET provides logic inverter to support low + level and falling edge interrupts. + +maintainers: + - Masahiro Yamada + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + enum: + - socionext,uniphier-ld4-aidet + - socionext,uniphier-pro4-aidet + - socionext,uniphier-sld8-aidet + - socionext,uniphier-pro5-aidet + - socionext,uniphier-pxs2-aidet + - socionext,uniphier-ld6b-aidet + - socionext,uniphier-ld11-aidet + - socionext,uniphier-ld20-aidet + - socionext,uniphier-pxs3-aidet + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: | + The first cell defines the interrupt number (corresponds to the SPI + interrupt number of GIC). The second cell specifies the trigger type as + defined in interrupts.txt in this directory. + const: 2 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + aidet: aidet@5fc20000 { + compatible = "socionext,uniphier-pro4-aidet"; + reg = <0x5fc20000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; -- 2.17.1