Received: by 2002:a25:1506:0:0:0:0:0 with SMTP id 6csp1936982ybv; Sun, 23 Feb 2020 18:53:01 -0800 (PST) X-Google-Smtp-Source: APXvYqwcvvNxrum+FA9PQvI4rM1wkXAudmrVttMiFnUdRu+CaH/JUsLrzso/sFI7QPn/6oefn+H2 X-Received: by 2002:a05:6830:1011:: with SMTP id a17mr36234133otp.45.1582512781378; Sun, 23 Feb 2020 18:53:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1582512781; cv=none; d=google.com; s=arc-20160816; b=kPd/3Rup1cg0t2xtEDV3N8mkuVa3UqhZ8rT/vpXhMsZxizmidXST2WNfqUUv4LGKDA QzVipVeXVI0S83Dk/looiuP6JKqbtfYpaWIpUCA8dhcA+ppGLEHmGfEMtMstoHWmZHZb Re/FYwgL++zzPpsEdE5b0IUJ74krQIKH1/Z9LdeJ184H7c/O1ADR7wobOsyx/KW+qV9+ M8tsK39IOYyjxziRRQ7yy3UhPbEWaTlT4y4y8EWbV90RrfIoE7/9jDiEPwmsilFHZkUd wxYn9HiQa7rp6eYEpWjOT9+aWlu4dYelT2MArZtQ9ByKUK5hh54fwG4vvfM/ApFcoSmr HNAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=4Gx/d5Tf7V0acVHCDug+iMHOjG7ea3A/p4aztk7ae5w=; b=d/ipbBjY1ZsodtBRlBxHOZfK6hEiM5kiL23ONoRM6Pmi376G1Bn2vpiHWIrg2tTb4/ PcmOf+9Fl91v78KJZ4F/wWl6DpeKpPzn7fRMeB6WB3E8UD7Sfx5c22xcyQBmbvuLGTLU 9O6WVGcvg6mloPSOwqiUqk5Ct70ohHiP3pR/0TyiEv5al4waSUud8FeIfqccHH0zCDbU ZXqyr3vHTmC/2o8b1az65wd28rFPAts/iVTlVdpHVhNpXb49w3iedMQcPuA4O76Ad8BO JiBzFRUNGGvSiWWDB4aHlVkpZnZv5BV4gHGj+oKw22B8+a/+dmJoodXVHnPh7LMF2r9K 43Lg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r82si4215233oie.116.2020.02.23.18.52.49; Sun, 23 Feb 2020 18:53:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727228AbgBXCvD (ORCPT + 99 others); Sun, 23 Feb 2020 21:51:03 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:43792 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727156AbgBXCvD (ORCPT ); Sun, 23 Feb 2020 21:51:03 -0500 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 08295B1E631B9B876FB6; Mon, 24 Feb 2020 10:51:01 +0800 (CST) Received: from DESKTOP-8RFUVS3.china.huawei.com (10.173.222.27) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.439.0; Mon, 24 Feb 2020 10:50:52 +0800 From: Zenghui Yu To: , CC: , , , Zenghui Yu , Yanlei Jia Subject: [PATCH] irqchip/gic-v3-its: Clear Valid before writing any bits else in VPENDBASER Date: Mon, 24 Feb 2020 10:50:29 +0800 Message-ID: <20200224025029.92-1-yuzenghui@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.173.222.27] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Valid bit must be cleared before changing anything else when writing GICR_VPENDBASER to avoid the UNPREDICTABLE behavior. This is exactly what we've done on 32bit arm, but not on arm64. This works fine on GICv4 where we only clear Valid for a vPE deschedule. With the introduction of GICv4.1, we might also need to talk something else (e.g., PendingLast, Doorbell) to the redistributor when clearing the Valid. Let's port the 32bit gicr_write_vpendbaser() to arm64 so that hardware can do the right thing after descheduling the vPE. Cc: Yanlei Jia Signed-off-by: Zenghui Yu --- arch/arm64/include/asm/arch_gicv3.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index 25fec4bde43a..effe66e1ca58 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -143,7 +143,18 @@ static inline u32 gic_read_rpr(void) #define gicr_write_vpropbaser(v, c) writeq_relaxed(v, c) #define gicr_read_vpropbaser(c) readq_relaxed(c) -#define gicr_write_vpendbaser(v, c) writeq_relaxed(v, c) +#define gicr_write_vpendbaser(v, c) do { \ + u64 tmp = readq_relaxed(c); \ + \ + /* Clear Valid before writing any bits else. */ \ + if (tmp & GICR_VPENDBASER_Valid) { \ + tmp &= ~GICR_VPENDBASER_Valid; \ + writeq_relaxed(tmp, c); \ + } \ + \ + writeq_relaxed(v, c); \ +} while (0) + #define gicr_read_vpendbaser(c) readq_relaxed(c) static inline bool gic_prio_masking_enabled(void) -- 2.19.1