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Subject: Re: [PATCH v10 1/2] dt-bindings: spi: Add schema for Cadence QSPI
 Controller driver
To:     "Ramuthevar, Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@linux.intel.com>,
        Rob Herring <robh+dt@kernel.org>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        linux-spi <linux-spi@vger.kernel.org>,
        Mark Brown <broonie@kernel.org>,
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        Dinh Nguyen <dinguyen@kernel.org>, <tien.fong.chee@intel.com>,
        =?UTF-8?Q?Marek_Va=c5=a1ut?= <marex@denx.de>,
        <cheol.yong.kim@intel.com>, <qi-ming.wu@intel.com>
References: <20200219022852.28065-1-vadivel.muruganx.ramuthevar@linux.intel.com>
 <20200219022852.28065-2-vadivel.muruganx.ramuthevar@linux.intel.com>
 <CAL_JsqKJky=y4nhECUFVzTYvEpjFoOH_6UY9uZG5bvBVWq=SYQ@mail.gmail.com>
 <64b7ab12-0c11-df25-95e7-ee62227ec7ec@linux.intel.com>
 <85178128-4906-8b1a-e3f1-ab7a36ff8c23@ti.com>
 <c119a70d-b7ef-ab1b-4590-7ac77395297f@linux.intel.com>
From:   Vignesh Raghavendra <vigneshr@ti.com>
Message-ID: <8c329860-84fd-463b-782f-83a788998878@ti.com>
Date:   Tue, 25 Feb 2020 16:30:21 +0530
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On 25/02/20 1:08 pm, Ramuthevar, Vadivel MuruganX wrote:
>>>>> +
>>>>> +  cdns,fifo-depth:
>>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>>> +    description:
>>>>> +      Size of the data FIFO in words.
>>>> A 4GB fifo is valid? Add some constraints.
>>> 128 is valid, will update.
>> Nope, the width of this field is 8bits -> 256 bytes 
> 
> correct me if I am wrong, the width of this field is 4bits -> 128 bytes
> (based on QUAD mode) .

This has nothing to do with quad-mode. Its about how much SRAM amount of
SRAM is present to buffer INDAC mode data. For TI platforms this is 256
bytes.
See CQSPI_REG_SRAMPARTITION definition in your datasheet.

-- 
Regards
Vignesh