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Wed, 26 Feb 2020 08:02:29 +0000 Date: Wed, 26 Feb 2020 10:02:26 +0200 From: Laurentiu Palcu To: Lucas Stach Cc: Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , agx@sigxcpu.org, lukas@mntmn.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: Re: [PATCH v3 4/4] arm64: dts: imx8mq: add DCSS node Message-ID: <20200226080226.xppukafx7453xm2d@fsr-ub1864-141> References: <1575625964-27102-1-git-send-email-laurentiu.palcu@nxp.com> <1575625964-27102-5-git-send-email-laurentiu.palcu@nxp.com> <5d0f20b76e31360372a410983b013551062e9a91.camel@pengutronix.de> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5d0f20b76e31360372a410983b013551062e9a91.camel@pengutronix.de> User-Agent: NeoMutt/20171215 X-ClientProxiedBy: LO2P265CA0310.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a5::34) To AM6PR04MB5766.eurprd04.prod.outlook.com (2603:10a6:20b:ab::15) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from fsr-ub1864-141 (89.37.124.34) by LO2P265CA0310.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a5::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2750.18 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: M+SwYr+swCDsHI3G6FgqooKf4A+dtz4TFZ8C8mIp0ZYGcS7tsHt6BqiX4/gZOMjFW82Kk9kPvvDzUL+Lt1xxP8r0aIJ5hcqrH9fr2FjB6UlkZ+tryGrx60vhOyvK4vkLXjXguTSrHuZqIgS3i1x0/Tn98qyQY0u9mj2Dt6T/yMLMD8ZjSqY6kjLIExv70B3XKU8VvnNNzHvLc76arSMYTiVs4O78s93+5Hx31uDZwz8+gPNMe+kiE1GwFWF9SfVBaNzWG7VAniCl1SbFRyFuoxUCyronPe3eJ0MpLUxs16EYuJuKIBqGj8FUZj+7RsiPaOPETYTcCgJlciQf6SQ5AUCjsAUGQc8rsC7qbMoDUUjxjJzOAhggQtmqsAzlHqCwwRXp45JmTiH+H5MvwjnVsiHj2wNNWVcB4zJB0GlH2eXUxRxd8f3XKXmOwyYcc+00p6HwajstRR9/Z+pEAyZmef0rx45LNfujI1G+LZL0eOE= X-MS-Exchange-AntiSpam-MessageData: eSTfkwJ7bTImUH3LlamRv+EsHsG1S0bPMqFP4Y0MvQ2GcBEDCrvxZHHjFd6O4ei+N2SFiRouAxxeG+pSsJN7dDFXtp4loiOtZut31CTuL/vfu1t1gnI2yPN1H2eBldYQ/PmfIGUG8JwbF0SUjVEx0w== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f663fe35-a783-48f3-a5ff-08d7ba9239e9 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2020 08:02:29.8068 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0PG4r0mktqvD+9xQ9MQ7w2iuJeKllXFBJ0pdYXwvsxhmFFPDyrXHp6Sl5iN3CFcuP+MIT+0yqzNEOpZzejJhew== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5510 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Lucas, On Mon, Feb 24, 2020 at 06:23:51PM +0100, Lucas Stach wrote: > On Fr, 2019-12-06 at 11:52 +0200, Laurentiu Palcu wrote: > > This patch adds the node for iMX8MQ Display Controller Subsystem. > > > > Signed-off-by: Laurentiu Palcu > > --- > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 25 +++++++++++++++++++++++++ > > 1 file changed, 25 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > index f6e840c..da7e485 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > @@ -981,6 +981,31 @@ > > interrupt-controller; > > #interrupt-cells = <1>; > > }; > > + > > + dcss: display-controller@32e00000 { > > Node address is lower than the irqsteer node, so the dcss node should > be added before, not after the irqsteer node in the DT. That's correct, I'll move it. > > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "nxp,imx8mq-dcss"; > > + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; > > + interrupts = <6>, <8>, <9>; > > + interrupt-names = "ctx_ld", "ctxld_kick", "vblank"; > > + interrupt-parent = <&irqsteer>; > > + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, > > + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, > > + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, > > + <&clk IMX8MQ_VIDEO2_PLL_OUT>, > > + <&clk IMX8MQ_CLK_DISP_DTRC>; > > + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; > > + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, > > + <&clk IMX8MQ_CLK_DISP_RTRM>, > > + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; > > + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, > > + <&clk IMX8MQ_SYS1_PLL_800M>, > > + <&clk IMX8MQ_CLK_27M>; > > + assigned-clock-rates = <800000000>, > > + <400000000>; > > Second line is not aligned to the first one. ack Thanks, laurentiu > > > + status = "disabled"; > > + }; > > }; > > > > gpu: gpu@38000000 { > -- Laurentiu NXP