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From:   Chen-Yu Tsai <wens@csie.org>
Date:   Thu, 27 Feb 2020 11:03:02 +0800
Message-ID: <CAGb2v67ka=7n0BHw_UDY4AH+PmvEJDTrr8JZUB2e5jCXdgSq3Q@mail.gmail.com>
Subject: Re: [PATCH] ARM: dts: sunxi: h3/h5: add r_pwm node
To:     Mans Rullgard <mans@mansr.com>
Cc:     Maxime Ripard <mripard@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        devicetree <devicetree@vger.kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
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On Thu, Feb 27, 2020 at 2:33 AM Mans Rullgard <mans@mansr.com> wrote:
>
> There is a second PWM unit available in the PL I/O block.
> Add a node and pinmux definition for it.
>
> Signed-off-by: Mans Rullgard <mans@mansr.com>
> ---
>  arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> index 107eeafad20a..1842c9f12c36 100644
> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> @@ -871,6 +871,19 @@
>                                 pins = "PL0", "PL1";
>                                 function = "s_i2c";
>                         };
> +
> +                       r_pwm_pins: r-pwm-pins {

Since it's just one pin, you could use the singular form instead.
And also set it as the default.

With that,

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

> +                               pins = "PL10";
> +                               function = "s_pwm";
> +                       };
> +               };
> +
> +               r_pwm: pwm@1f03800 {
> +                       compatible = "allwinner,sun8i-h3-pwm";
> +                       reg = <0x01f03800 0x8>;
> +                       clocks = <&osc24M>;
> +                       #pwm-cells = <3>;
> +                       status = "disabled";
>                 };
>         };
>  };
> --
> 2.25.0
>
>
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