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From:   Fawad Lateef <fawadlateef@gmail.com>
Date:   Fri, 28 Feb 2020 11:27:00 +0100
Message-ID: <CAGgoGu5S0Yr5j1yegjkgbqXvdtwaCvX6=hnKt+z7F5+qVXi96Q@mail.gmail.com>
Subject: Re: Help needed in understanding weird PCIe issue on imx6q (PCIe just
 goes bad)
To:     Fabio Estevam <festevam@gmail.com>
Cc:     Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        linux-pci@vger.kernel.org
Content-Type: multipart/mixed; boundary="000000000000ca31da059fa047ab"
Sender: linux-kernel-owner@vger.kernel.org
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--000000000000ca31da059fa047ab
Content-Type: text/plain; charset="UTF-8"

Hi Fabio,

On Thu, 27 Feb 2020 at 00:40, Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Fawad,
>
> On Sat, Feb 22, 2020 at 12:26 PM Fawad Lateef <fawadlateef@gmail.com> wrote:
> >
> > Hello,
> >
> > I am trying to figure-out an issue on our i.MX6Q platform based design
> > where PCIe interface goes bad.
> >
> > We have a Phytec i.MX6Q eMMC SOM, attached to our custom designed
> > board. PCIe root-complex from i.MX6Q is attached to PLX switch
> > (PEX8605).
> >
> > Linux kernel version is 4.19.9x and also 4.14.134 (from phytec's
>
> Does it happen with 5.4 or 5.5 too?

I had 5.2.xx kernel working earlier but then due to other issues I
switched back to Phytec provided kernel. I will give 5.2.xx (as its
patched for SOM already on my system) a try again and see if its
better.

>
> Which dts are you using?

I attached the dts files by mail. Though I tried on another OEM som
"Embedded ARtists" i.MX6Q with their own dts (but reset-gpio setting
for mPCIe card commented out) quickly and saw similar behaviour.

>
> > Then I enable the #PERST pin of PLX switch, everything is still good
> > (no rescan on Linux is done yet)
> >
> > ~ # echo 139 > /sys/class/gpio/export
> > ~ # echo out > /sys/class/gpio/gpio139/direction
> > ~ # echo 1 > /sys/class/gpio/gpio139/value
>
> Not sure why you toggle the PERST pin from userspace.

I am trying to do this later from user-space as we are battery
operated WLAN AP device and only want to enable devices based on
different "modes"; like on batteries we do not want USB3 controller
active and also might just enable one of the two WLANs etc.

>
> You should do it via reset-gpio property in the device tree.

I tried to enable only PLX switch with reset-gpio and I see that later
when I try to enable WLANs and do pci->rescan then WLANs unable to
allocate memory in BAR regions. Likely as we do not have PCIe hot-plug
enabled. On ARM without BIOS/bootloader doing enumeration it might be
even useful, right?

~ # echo 1 > /sys/bus/pci/rescan
[ 2280.186261] pcieport 0000:02:02.0: BAR 8: no space for [mem size 0x00300000]
[ 2280.193409] pcieport 0000:02:02.0: BAR 8: failed to assign [mem
size 0x00300000]
[ 2280.200834] pcieport 0000:02:03.0: BAR 8: no space for [mem size 0x00300000]
[ 2280.207948] pcieport 0000:02:03.0: BAR 8: failed to assign [mem
size 0x00300000]
[ 2280.215456] pci 0000:04:00.0: BAR 0: no space for [mem size 0x00200000 64bit]
[ 2280.222690] pci 0000:04:00.0: BAR 0: failed to assign [mem size
0x00200000 64bit]
[ 2280.230206] pci 0000:04:00.0: BAR 6: no space for [mem size 0x00010000 pref]
[ 2280.237321] pci 0000:04:00.0: BAR 6: failed to assign [mem size
0x00010000 pref]
[ 2280.244886] pci 0000:05:00.0: BAR 0: no space for [mem size 0x00200000 64bit]
[ 2280.252115] pci 0000:05:00.0: BAR 0: failed to assign [mem size
0x00200000 64bit]
[ 2280.259623] pci 0000:05:00.0: BAR 6: no space for [mem size 0x00010000 pref]
[ 2280.266729] pci 0000:05:00.0: BAR 6: failed to assign [mem size
0x00010000 pref]

By the way is there way to specify multiple "gpio-reset" pins in
device tree? Is reset-gpio property can have multiple pins OR
reset-gpios is to be used and its similar to gpio-reset (without 's')
property?

Thanks,

Fawad Lateef

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