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[209.132.180.67]) by mx.google.com with ESMTP id m4si1560869otr.64.2020.03.04.09.04.54; Wed, 04 Mar 2020 09:05:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730032AbgCDRDY (ORCPT + 99 others); Wed, 4 Mar 2020 12:03:24 -0500 Received: from foss.arm.com ([217.140.110.172]:37294 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726915AbgCDRDY (ORCPT ); Wed, 4 Mar 2020 12:03:24 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6697E31B; Wed, 4 Mar 2020 09:03:23 -0800 (PST) Received: from bogus (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3073A3F6CF; Wed, 4 Mar 2020 09:03:22 -0800 (PST) Date: Wed, 4 Mar 2020 17:03:20 +0000 From: Sudeep Holla To: Peng Fan Cc: "robh+dt@kernel.org" , "viresh.kumar@linaro.org" , "f.fainelli@gmail.com" , dl-linux-imx , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Sudeep Holla Subject: Re: [PATCH V4 2/2] firmware: arm_scmi: add smc/hvc transport Message-ID: <20200304170319.GB44525@bogus> References: <1583201219-15839-1-git-send-email-peng.fan@nxp.com> <1583201219-15839-3-git-send-email-peng.fan@nxp.com> <20200304103954.GA25004@bogus> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Peng, On Wed, Mar 04, 2020 at 02:16:00PM +0000, Peng Fan wrote: > > Subject: RE: [PATCH V4 2/2] firmware: arm_scmi: add smc/hvc transport > > > > Hi Sudeep, > > > > > Subject: Re: [PATCH V4 2/2] firmware: arm_scmi: add smc/hvc transport > > > > > > On Tue, Mar 03, 2020 at 10:06:59AM +0800, peng.fan@nxp.com wrote: > > > > From: Peng Fan > > > > > > > > Take arm,smc-id as the 1st arg, leave the other args as zero for now. > > > > There is no Rx, only Tx because of smc/hvc not support Rx. > > > > > > > > Signed-off-by: Peng Fan > > > > > > [...] > > > > > > > +static int smc_send_message(struct scmi_chan_info *cinfo, > > > > + struct scmi_xfer *xfer) > > > > +{ > > > > + struct scmi_smc *scmi_info = cinfo->transport_info; > > > > + struct arm_smccc_res res; > > > > + > > > > + shmem_tx_prepare(scmi_info->shmem, xfer); > > > > > > How do we protect another thread/process on another CPU going and > > > modifying the same shmem with another request ? We may need notion of > > > channel with associated shmem and it is protected with some lock. > > > > This is valid concern. But I think if shmem is shared bwteen protocols, the > > access to shmem should be protected in > > drivers/firmware/arm_scmi/driver.c: scmi_do_xfer, because send_message > > and fetch_response both touches shmem > > > > The mailbox transport also has the issue you mentioned, I think. No, it doesn't. I hope you realised that now based on your statement below. > > Ignore my upper comments. How do think the following diff based on current patch? > > If ok, I'll squash it with current patch and send out v5. > > diff --git a/drivers/firmware/arm_scmi/smc.c b/drivers/firmware/arm_scmi/smc.c > index 88f91b68f297..7d770112f339 100644 > --- a/drivers/firmware/arm_scmi/smc.c > +++ b/drivers/firmware/arm_scmi/smc.c > @@ -29,6 +29,8 @@ struct scmi_smc { > u32 func_id; > }; > > +static DEFINE_MUTEX(smc_mutex); > + > static bool smc_chan_available(struct device *dev, int idx) > { > return true; > @@ -99,11 +101,15 @@ static int smc_send_message(struct scmi_chan_info *cinfo, > struct scmi_smc *scmi_info = cinfo->transport_info; > struct arm_smccc_res res; > > + mutex_lock(&smc_mutex); > + > shmem_tx_prepare(scmi_info->shmem, xfer); > > arm_smccc_1_1_invoke(scmi_info->func_id, 0, 0, 0, 0, 0, 0, 0, &res); > scmi_rx_callback(scmi_info->cinfo, shmem_read_header(scmi_info->shmem)); > > + mutex_unlock(&smc_mutex); > + > return res.a0; > } > Yes, this may fix the issue. However I would like to know if we need to support multiple channels/shared memory simultaneously. It is fair requirement and may need some work which should be fine. I just want to make sure we don't need anything more from DT or if we need to add more to DT bindings, we need to ensure it won't break single channel. I will think about that, but I would like to hear from other users of this SMC for SCMI. -- Regards, Sudeep