Received: by 2002:a25:c205:0:0:0:0:0 with SMTP id s5csp5460774ybf; Thu, 5 Mar 2020 01:08:24 -0800 (PST) X-Google-Smtp-Source: ADFU+vtC8AqzpQmPAJToNgg12ufpPV+o3PfiALt/YOHLcgX1Ua9qDdc/uEBxqp3VxE6y+16lkEll X-Received: by 2002:a9d:ecc:: with SMTP id 70mr5699637otj.182.1583399303946; Thu, 05 Mar 2020 01:08:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1583399303; cv=none; d=google.com; s=arc-20160816; b=IzXvP5l8MQuBqI6KXCdKBVqwjByX3AFzw9iT80iVDdqu6T0zhaMcV7hdOd7Yast8lU 6Shc3QJLtOKdUg4e2+ndO6IRTwAh317N7OmqcyjOiGuHg3LT5MOlopiycij0nuXaJW0H j7KldzUilubpCgbnI01P42TJLCbJUMFckqWVarkONwkWgHTr8Dlk5l8+kZdWjO9bnXjl MjlPjzc9v5Fc/571b9YWvRlGVVMJLuXEL9ZlYlGIcQ8NygZhGzQ6SyLW5VVV1DDuUU/F e/R56mzOZ8pxSy71VVhZtE/j8e7BVErEehSuu8yLxmxmqXWuIlRqbuI1aaAHolZzPF9n Oegw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=1iTEiNBAF0ixdNZ4utN4vIOlr+87ikfpM1JZ0YRDens=; b=Q6/X0czNBc98izs7vKlzgPQGxOvGrc86Z/T+3t8BmYwV1Uajq+c3JFQul7TD4ftfz2 Y8i6uHunLV9RVTQa2PNQ6jAvNTZNFuO4cAyXBCiW6BodM8CGeVTvKCroMQIKlnRJWtqx BwYtWQ3YcFeL0VB+bytDt2+RYGPA1zveOKaCA+ECY0N+7ZO9ewIxfXmprVFekwn30UqK EIrUARkTPEzh1rzsph63cLl5MnXDo0V9qQmG4z6lA7SRVvPnf2rFsb4uMU/Hoc5Z3oio Wo7MEesdZSXuftgrLCm7hdKLKUkYvcZbKkrzD6CeaWurzZytXb5uRAEq309oikREHe+9 f8xQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l15si3275435oig.146.2020.03.05.01.08.12; Thu, 05 Mar 2020 01:08:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727126AbgCEJHY (ORCPT + 99 others); Thu, 5 Mar 2020 04:07:24 -0500 Received: from foss.arm.com ([217.140.110.172]:45250 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727121AbgCEJHV (ORCPT ); Thu, 5 Mar 2020 04:07:21 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8C7634B2; Thu, 5 Mar 2020 01:07:20 -0800 (PST) Received: from e108754-lin.cambridge.arm.com (e108754-lin.cambridge.arm.com [10.1.198.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 117C43F534; Thu, 5 Mar 2020 01:07:17 -0800 (PST) From: Ionela Voinescu To: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, suzuki.poulose@arm.com, sudeep.holla@arm.com, lukasz.luba@arm.com, valentin.schneider@arm.com, dietmar.eggemann@arm.com, rjw@rjwysocki.net, pkondeti@codeaurora.org, ionela.voinescu@arm.com Cc: peterz@infradead.org, mingo@redhat.com, vincent.guittot@linaro.org, viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v6 7/7] clocksource/drivers/arm_arch_timer: validate arch_timer_rate Date: Thu, 5 Mar 2020 09:06:27 +0000 Message-Id: <20200305090627.31908-8-ionela.voinescu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200305090627.31908-1-ionela.voinescu@arm.com> References: <20200305090627.31908-1-ionela.voinescu@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Using an arch timer with a frequency of less than 1MHz can potentially result in incorrect functionality in systems that assume a reasonable rate of the arch timer of 1 to 50MHz, described as typical in the architecture specification. Therefore, warn if the arch timer rate is below 1MHz, which is considered atypical and worth emphasizing. Signed-off-by: Ionela Voinescu Suggested-by: Valentin Schneider Acked-by: Marc Zyngier Cc: Mark Rutland Cc: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 9a5464c625b4..4faa930eabf8 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -885,6 +885,17 @@ static int arch_timer_starting_cpu(unsigned int cpu) return 0; } +static int validate_timer_rate(void) +{ + if (!arch_timer_rate) + return -EINVAL; + + /* Arch timer frequency < 1MHz can cause trouble */ + WARN_ON(arch_timer_rate < 1000000); + + return 0; +} + /* * For historical reasons, when probing with DT we use whichever (non-zero) * rate was probed first, and don't verify that others match. If the first node @@ -900,7 +911,7 @@ static void arch_timer_of_configure_rate(u32 rate, struct device_node *np) arch_timer_rate = rate; /* Check the timer frequency. */ - if (arch_timer_rate == 0) + if (validate_timer_rate()) pr_warn("frequency not available\n"); } @@ -1594,9 +1605,10 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table) * CNTFRQ value. This *must* be correct. */ arch_timer_rate = arch_timer_get_cntfrq(); - if (!arch_timer_rate) { + ret = validate_timer_rate(); + if (ret) { pr_err(FW_BUG "frequency not available.\n"); - return -EINVAL; + return ret; } arch_timer_uses_ppi = arch_timer_select_ppi(); -- 2.17.1