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From:   Ulf Hansson <ulf.hansson@linaro.org>
Date:   Thu, 5 Mar 2020 16:17:57 +0100
Message-ID: <CAPDyKFr=hE6diZmaVy-os3rFScHe+8OphBS+edkVGK+Z-J_=HA@mail.gmail.com>
Subject: Re: [PATCH] mmc: mmc: Fix the timing for clock changing in mmc
To:     "Seo, Kyungmin" <kyungmin.seo@intel.com>,
        Adrian Hunter <adrian.hunter@intel.com>,
        Chaotian Jing <chaotian.jing@mediatek.com>
Cc:     "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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+ Adrian, Chaotian

On Thu, 5 Mar 2020 at 09:57, Seo, Kyungmin <kyungmin.seo@intel.com> wrote:
>
> The mmc_hs400_to_hs200 function is called only in HS400 mode.
> I saw the clock change from 200MHz to 52MHz via oscilloscope on real platform.
>
> I think CMD6 is sent in HS400 mode with 200MHz clock, but it's not.
> First CMD6 in mmc_hs400_to_hs200 function is sent with 52MHz clock.

I had a vague memory that we have discussed a similar problem as your
are pointing out on the mailing list already. And I was right.

Please read up on the below references, [1], [2] for the earlier
discussions. I suggested a solution for Chaotian to try, but it seems
like he never managed to give it a go, as I don't recall new patch
being posted.

Perhaps you can pick up were Chaotian left and see if you can
implement the suggested solution(s). My main concern is breaking other
host drivers, as that seems quite likely to happen, if we aren't
careful about this.

Kind regards
Uffe

[1]
https://lore.kernel.org/linux-mmc/1548921212-5219-1-git-send-email-chaotian.jing@mediatek.com/
[2]
https://lore.kernel.org/linux-mmc/CAPDyKFquyyXx1MqNLVXuFxcEDB9nKzN8LGGNUP2yxoVMQrWiUg@mail.gmail.com/


>
> Thanks
> KM
>
> -----Original Message-----
> From: Ulf Hansson <ulf.hansson@linaro.org>
> Sent: Wednesday, March 4, 2020 8:09 PM
> To: Seo, Kyungmin <kyungmin.seo@intel.com>
> Cc: linux-mmc@vger.kernel.org; Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH] mmc: mmc: Fix the timing for clock changing in mmc
>
> On Wed, 12 Feb 2020 at 03:40, Kyungmin Seo <kyungmin.seo@intel.com> wrote:
> >
> > The clock has to be changed after sending CMD6 for HS mode selection
> > in
> > mmc_hs400_to_hs200() function.
> >
> > The JEDEC 5.0 and 5.1 said that "High-speed" mode selection has to
> > enable the the high speed mode timing in the Device, before chaning
> > the clock frequency to a frequency between 26MHz and 52MHz.
>
> I think that is based upon the assumption that you are using a lower frequency to start with.
>
> For example, assume that you are running with 400KHz during card initialization, then you want to send the CMD6 to switch to HS mode and that should be done, before updating the clock rate.
>
> mmc_hs400_to_hs200() goes the opposite direction, so I think the current code looks correct to me.
>
> Kind regards
> Uffe
>
> >
> > Signed-off-by: Kyungmin Seo <kyungmin.seo@intel.com>
> > ---
> >  drivers/mmc/core/mmc.c | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index
> > 3486bc7fbb64..98640b51c73e 100644
> > --- a/drivers/mmc/core/mmc.c
> > +++ b/drivers/mmc/core/mmc.c
> > @@ -1196,10 +1196,6 @@ int mmc_hs400_to_hs200(struct mmc_card *card)
> >         int err;
> >         u8 val;
> >
> > -       /* Reduce frequency to HS */
> > -       max_dtr = card->ext_csd.hs_max_dtr;
> > -       mmc_set_clock(host, max_dtr);
> > -
> >         /* Switch HS400 to HS DDR */
> >         val = EXT_CSD_TIMING_HS;
> >         err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
> > EXT_CSD_HS_TIMING, @@ -1210,6 +1206,10 @@ int
> > mmc_hs400_to_hs200(struct mmc_card *card)
> >
> >         mmc_set_timing(host, MMC_TIMING_MMC_DDR52);
> >
> > +       /* Reduce frequency to HS */
> > +       max_dtr = card->ext_csd.hs_max_dtr;
> > +       mmc_set_clock(host, max_dtr);
> > +
> >         err = mmc_switch_status(card);
> >         if (err)
> >                 goto out_err;
> > --
> > 2.17.1
> >