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[209.132.180.67]) by mx.google.com with ESMTP id k8si116326oib.47.2020.03.05.13.12.24; Thu, 05 Mar 2020 13:12:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20161025 header.b=Xo9Ym8or; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726368AbgCEVLJ (ORCPT + 99 others); Thu, 5 Mar 2020 16:11:09 -0500 Received: from mail-io1-f65.google.com ([209.85.166.65]:38818 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726049AbgCEVLJ (ORCPT ); Thu, 5 Mar 2020 16:11:09 -0500 Received: by mail-io1-f65.google.com with SMTP id s24so8049252iog.5 for ; Thu, 05 Mar 2020 13:11:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=KgCiuleqCzLTSUjw22UCoY8ZDkk7GEszoFBVAof0Qx8=; b=Xo9Ym8orTM9HyxCSsaVHy9BymP4VD2UA8iON1jyOyciEx7yuFQ2g6QIf+oCNtf3VKB L/dwI6a2LpncfRwMifkF/UcA8o+ZXg2lCnfetTi8RqtExWq6NT0pp+2s5lAlI/Ej3nSb ccGVm74s6E1eaTDrvIiWu+2HxhA33gA48NvkSqC6zF5Ae6/mJw9iQHKLYZqw63z6edrd cziYbZqVklcKZ6z/wmuqPO/FTFVC6UaIpNJITYpFTRb7TEKJOQqc5hnSoEdeSWg5fwCg tHRmvbiyNZt7al5MhrpYknx7AuhpQOiBzg59pdlxXJ+i6IH24NDX4+2b5peE26utXGBv oEoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=KgCiuleqCzLTSUjw22UCoY8ZDkk7GEszoFBVAof0Qx8=; b=n4pAFzYkpFrT0ktsKIlwPeZqJ3PGRpdTlUnwt7UY+rO3aRK49XN25/rnfNxL6T7Sf/ MhkL8a9/A3JQcgvqvBncMowwVvL+JYArywZQ9D3SpYwFJxBBc3vuZbYjRzRf/jhGqpkq sHvFx+eoiDsqVqsWOrGOrT+mHgFavGcsEsjNo5e3OHkuF0YW3nDgE3Ai/HaxzIQl9/4R 2Okr8pYdEgXskfUclWDC2+Qbc2Eq912YzaOodMnnCZzvLsJqNtcgBehNsBuFm2jUAsGw ieyqPj9yEMJ9KfBR+uLRaoIPiIfOJ4J/aupcbrgjLBg7P4NArXze6y2H/Vyh/LDj1LF0 gt/A== X-Gm-Message-State: ANhLgQ2mScvciwfxTviSF6D6na5Z+1mwFUDyXohCO5B9r0X7vTAqdg3n Hl3+6323WnnSXS14mzOzXoz49dLbF+BpzLHHHdVA6w== X-Received: by 2002:a05:6602:27cf:: with SMTP id l15mr313933ios.70.1583442668601; Thu, 05 Mar 2020 13:11:08 -0800 (PST) MIME-Version: 1.0 References: <20200305013437.8578-1-sean.j.christopherson@intel.com> <20200305013437.8578-5-sean.j.christopherson@intel.com> <20200305192532.GN11500@linux.intel.com> In-Reply-To: <20200305192532.GN11500@linux.intel.com> From: Jim Mattson Date: Thu, 5 Mar 2020 13:10:57 -0800 Message-ID: Subject: Re: [PATCH v2 4/7] KVM: x86: Fix CPUID range checks for Hypervisor and Centaur classes To: Sean Christopherson Cc: Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , kvm list , LKML , Pu Wen Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 5, 2020 at 11:25 AM Sean Christopherson wrote: > > On Thu, Mar 05, 2020 at 10:43:51AM -0800, Jim Mattson wrote: > > On Wed, Mar 4, 2020 at 5:34 PM Sean Christopherson > > wrote: > > > > > > Rework the masking in the out-of-range CPUID logic to handle the > > > Hypervisor sub-classes, as well as the Centaur class if the guest > > > virtual CPU vendor is Centaur. > > > > > > Masking against 0x80000000 only handles basic and extended leafs, which > > > results in Hypervisor range checks being performed against the basic > > > CPUID class, and Centuar range checks being performed against the > > > Extended class. E.g. if CPUID.0x40000000.EAX returns 0x4000000A and > > > there is no entry for CPUID.0x40000006, then function 0x40000006 would > > > be incorrectly reported as out of bounds. > > > > > > While there is no official definition of what constitutes a class, the > > > convention established for Hypervisor classes effectively uses bits 31:8 > > > as the mask by virtue of checking for different bases in increments of > > > 0x100, e.g. KVM advertises its CPUID functions starting at 0x40000100 > > > when HyperV features are advertised at the default base of 0x40000000. > > > > > > The bad range check doesn't cause functional problems for any known VMM > > > because out-of-range semantics only come into play if the exact entry > > > isn't found, and VMMs either support a very limited Hypervisor range, > > > e.g. the official KVM range is 0x40000000-0x40000001 (effectively no > > > room for undefined leafs) or explicitly defines gaps to be zero, e.g. > > > Qemu explicitly creates zeroed entries up to the Cenatur and Hypervisor > > > limits (the latter comes into play when providing HyperV features). > > > > > > The bad behavior can be visually confirmed by dumping CPUID output in > > > the guest when running Qemu with a stable TSC, as Qemu extends the limit > > > of range 0x40000000 to 0x40000010 to advertise VMware's cpuid_freq, > > > without defining zeroed entries for 0x40000002 - 0x4000000f. > > > > > > Note, documentation of Centaur/VIA CPUs is hard to come by. Designating > > > 0xc0000000 - 0xcfffffff as the Centaur class is a best guess as to the > > > behavior of a real Centaur/VIA CPU. > > > > Don't forget Transmeta's CPUID range at 0x80860000 through 0x8086FFFF! > > Hmm, is it actually needed here? KVM doesn't advertise support for that > range in KVM_GET_SUPPORTED_CPUID. That's also why I limited the Centaur > range to vendor==CENTAUR, as KVM_GET_SUPPORTED_CPUID enumerates the > Centaur range if and only if the host CPU is Centaur. Ah. So cross-vendor CPUID specifications are not supported?