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Date:   Fri, 6 Mar 2020 10:52:08 +0000
From:   Russell King - ARM Linux admin <linux@armlinux.org.uk>
To:     Philippe Schenker <philippe.schenker@toradex.com>
Cc:     "linux-imx@nxp.com" <linux-imx@nxp.com>,
        "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
        "festevam@gmail.com" <festevam@gmail.com>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "tglx@linutronix.de" <tglx@linutronix.de>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "kstewart@linuxfoundation.org" <kstewart@linuxfoundation.org>,
        "allison@lohutok.net" <allison@lohutok.net>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>
Subject: Re: [PATCH] ARM: mach-imx6q: add ksz9131rn_phy_fixup
Message-ID: <20200306105208.GG25745@shell.armlinux.org.uk>
References: <20200305134928.19775-1-philippe.schenker@toradex.com>
 <20200305135346.GD25745@shell.armlinux.org.uk>
 <98f5901a121b83d4f7d75f9a9056bd3719e2ee89.camel@toradex.com>
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On Fri, Mar 06, 2020 at 09:57:15AM +0000, Philippe Schenker wrote:
> On Thu, 2020-03-05 at 13:53 +0000, Russell King - ARM Linux admin wrote:
> > On Thu, Mar 05, 2020 at 02:49:28PM +0100, Philippe Schenker wrote:
> > > The MAC of the i.MX6 SoC is compliant with RGMII v1.3. The KSZ9131
> > > PHY
> > > is like KSZ9031 adhering to RGMII v2.0 specification. This means the
> > > MAC should provide a delay to the TXC line. Because the i.MX6 MAC
> > > does
> > > not provide this delay this has to be done in the PHY.
> > > 
> > > This patch adds by default ~1.6ns delay to the TXC line. This should
> > > be good for all boards that have the RGMII signals routed with the
> > > same length.
> > > 
> > > The KSZ9131 has relatively high tolerances on skew registers from
> > > MMD 2.4 to MMD 2.8. Therefore the new DLL-based delay of 2ns is used
> > > and then as little as possibly subtracted from that so we get more
> > > accurate delay. This is actually needed because the i.MX6 SoC has
> > > an asynchron skew on TXC from -100ps to 900ps, to get all RGMII
> > > values within spec.
> > > 
> > > Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> > > 
> > > ---
> > > 
> > >  arch/arm/mach-imx/mach-imx6q.c | 37
> > > ++++++++++++++++++++++++++++++++++
> > >  1 file changed, 37 insertions(+)
> > > 
> > > diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-
> > > imx/mach-imx6q.c
> > > index edd26e0ffeec..8ae5f2fa33e2 100644
> > > --- a/arch/arm/mach-imx/mach-imx6q.c
> > > +++ b/arch/arm/mach-imx/mach-imx6q.c
> > > @@ -61,6 +61,14 @@ static void mmd_write_reg(struct phy_device *dev,
> > > int device, int reg, int val)
> > >  	phy_write(dev, 0x0e, val);
> > >  }
> > >  
> > > +static int mmd_read_reg(struct phy_device *dev, int device, int
> > > reg)
> > > +{
> > > +	phy_write(dev, 0x0d, device);
> > > +	phy_write(dev, 0x0e, reg);
> > > +	phy_write(dev, 0x0d, (1 << 14) | device);
> > > +	return phy_read(dev, 0x0e);
> > > +}
> > 
> > These look like the standard MII MMD registers, and it also looks like
> > you're reinventing phy_read_mmd() - but badly due to lack of locking.
> > 
> > I guess you need this because phy_read_mmd() may be modular - maybe
> > we should arrange for the accessors to be separately buildable into
> > the kernel, so that such fixups can stop badly reinventing the wheel?
> 
> Yes, I did that because of two reasons:
> 1. I tried phy_read_mmd() and phy_write_mmd() but this panic'd

That is because phydev->drv->read_mmd and phydev->drv is NULL at this
point.  There has been a patch around to solve that though.

> 2. There is already mmd_write_reg in that code so I thought it would be
> no big deal to also have a read in there.
> 
> But yeah, you're right that mmd_write_reg is from 2013...
> 
> How do you suggest to implement that?
> 
> Philippe

-- 
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