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Date:   Fri, 6 Mar 2020 11:16:20 +0000
From:   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To:     Bharat Kumar Gogada <bharatku@xilinx.com>
Cc:     "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
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        Ravikiran Gummaluri <rgummal@xilinx.com>,
        "maz@kernel.org" <maz@kernel.org>
Subject: Re: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
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On Fri, Feb 28, 2020 at 12:48:48PM +0000, Bharat Kumar Gogada wrote:
> > Subject: Re: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
> > 
> > [+MarcZ, FHI]
> > 
> > On Tue, Feb 25, 2020 at 02:39:56PM +0000, Bharat Kumar Gogada wrote:
> > 
> > [...]
> > 
> > > > > +/* ECAM definitions */
> > > > > +#define ECAM_BUS_NUM_SHIFT		20
> > > > > +#define ECAM_DEV_NUM_SHIFT		12
> > > >
> > > > You don't need these ECAM_* defines, you can use pci_generic_ecam_ops.
> > > Does this need separate ranges region for ECAM space ?
> > > We have ECAM and controller space in same region.
> > 
> > You can create an ECAM window with pci_ecam_create where *cfgres
> > represent the ECAM area, I don't get what you mean by "same region".
> > 
> > Do you mean "contiguous" ? Or something else ?
> Yes, contiguous; within ECAM region some space is for controller registers.

What does that mean ? I don't get it. Can you explain to me how this
address space works please ?

Thanks,
Lorenzo