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From:   Bharat Kumar Gogada <bharatku@xilinx.com>
To:     "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>
CC:     "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
        Ravikiran Gummaluri <rgummal@xilinx.com>,
        "maz@kernel.org" <maz@kernel.org>
Subject: RE: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
Thread-Topic: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
Thread-Index: AQHV14gyqXPkldKNt0SLTelX37u03Kgr8Z6AgAAlV5CABIIlAIAAIZtQgArnjQCAAAJtIA==
Date:   Fri, 6 Mar 2020 11:45:47 +0000
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> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: Friday, March 6, 2020 4:46 PM
> To: Bharat Kumar Gogada <bharatku@xilinx.com>
> Cc: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; Ravikiran Gummaluri <rgummal@xilinx.com>;
> maz@kernel.org
> Subject: Re: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port dri=
ver
>=20
> On Fri, Feb 28, 2020 at 12:48:48PM +0000, Bharat Kumar Gogada wrote:
> > > Subject: Re: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root
> > > Port driver
> > >
> > > [+MarcZ, FHI]
> > >
> > > On Tue, Feb 25, 2020 at 02:39:56PM +0000, Bharat Kumar Gogada wrote:
> > >
> > > [...]
> > >
> > > > > > +/* ECAM definitions */
> > > > > > +#define ECAM_BUS_NUM_SHIFT		20
> > > > > > +#define ECAM_DEV_NUM_SHIFT		12
> > > > >
> > > > > You don't need these ECAM_* defines, you can use
> pci_generic_ecam_ops.
> > > > Does this need separate ranges region for ECAM space ?
> > > > We have ECAM and controller space in same region.
> > >
> > > You can create an ECAM window with pci_ecam_create where *cfgres
> > > represent the ECAM area, I don't get what you mean by "same region".
> > >
> > > Do you mean "contiguous" ? Or something else ?
> > Yes, contiguous; within ECAM region some space is for controller regist=
ers.
>=20
> What does that mean ? I don't get it. Can you explain to me how this addr=
ess
> space works please ?
>=20
Hi Lorenzo,
		reg =3D <0x6 0x00000000 0x0 0x1000000>,
		      <0x0 0xFCA10000 0x0 0x1000>;
		reg-names =3D "cfg", "cpm_slcr";

In the above cfg region some region of it reserved for bridge registers and=
 rest for ECAM=20
address space transactions. The bridge registers are mapped at an unused of=
fset in config space
of root port, when the offset hit it will access controller register space.

This region is already being mapped=20
res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
port->reg_base =3D devm_ioremap_resource(dev, res);

Does pci_ecam_create will work along with above API simultaneously ?

Regards,
Bharat=20