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[209.132.180.67]) by mx.google.com with ESMTP id z18si239221oid.247.2020.03.06.05.39.26; Fri, 06 Mar 2020 05:39:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o41Jqr5J; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726740AbgCFNiD (ORCPT + 99 others); Fri, 6 Mar 2020 08:38:03 -0500 Received: from mail-vk1-f193.google.com ([209.85.221.193]:34396 "EHLO mail-vk1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726382AbgCFNiD (ORCPT ); Fri, 6 Mar 2020 08:38:03 -0500 Received: by mail-vk1-f193.google.com with SMTP id w67so608195vkf.1 for ; Fri, 06 Mar 2020 05:38:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=pRT33IXafqSAr33qlx5s+Y+vRzyqKbOBrTN3ps1thPQ=; b=o41Jqr5JyVJfTo5kWfFMhZB6OVZvxSSgEV43vr8hiKBBdUTzzbSHcILHK7E46FqCV1 zGC+1sXbOK83HkqScxPrT6ygSj3chMcPk56a4HEO1Hp+bQXUDtH7V2yqvRnGeZW5pe9P jZW98ry2S97rX+M3h+lwfREUocO47zlFRvfuZAsA4yxvw+5elom8/uXei4G2XdQr9NTQ KXEg/Hceo7Z1r5ffwG0Aj+jD3m3pPpd818wWRijHKlVbTZn970ZtZdrv5e9UWWjnH9I5 EMuEM90i5rNHhgH7P/cUgCRy/H0vpyq37zemCZXiDEbx1/fl29EQtXHEes0aFeL5V+MZ OW7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=pRT33IXafqSAr33qlx5s+Y+vRzyqKbOBrTN3ps1thPQ=; b=g4+l+jRhwnSDn5SEoz7gk6rVmcdgCzc4O5NPOFdGOQ1h956goZPId7uD/RipD9OEys tGN9TSUL/LOYTFGh2wfmLfUI5I0nVZAhAQCpkKy9PNsBP/OKnHaFNBh7PL2FwhqzaDf5 lzT4QwUIJ+kGbmtD3YzwHEPq5zzD7Dj9u5KJY11wCM20ZZV+wGKH+of/7J8XQrz8hAsT /NtGmUvSrKsMGDqzX9h8ncaBZiFkT0a8emtmV7dYxPwtPZ3Bhf1m74P4j0PS7hpttgDC GS9kDvtJRhx8DeAxZaz5M4I3zbwghDO469GLqC62izwB9T5DukPa8nEl6lQXBFaBC59A dvQw== X-Gm-Message-State: ANhLgQ2vQyR9Eb5y/vQ+Jr+1HSH4GfZ74zkP+DrrK2h6skD3yykYLkbo /p3tCEY0mU8yTnEbz57l3YrDKmE9IwFIU2phZS5/8g== X-Received: by 2002:a1f:78c5:: with SMTP id t188mr1669349vkc.43.1583501881058; Fri, 06 Mar 2020 05:38:01 -0800 (PST) MIME-Version: 1.0 References: <20200224231841.26550-1-digetx@gmail.com> <20200224231841.26550-4-digetx@gmail.com> <44c22925-a14e-96d0-1f93-1979c0c60525@wwwdotorg.org> <824a4d5f-8280-8860-3e80-68188a13aa3d@gmail.com> In-Reply-To: <824a4d5f-8280-8860-3e80-68188a13aa3d@gmail.com> From: Ulf Hansson Date: Fri, 6 Mar 2020 14:37:24 +0100 Message-ID: Subject: Re: [PATCH v1 3/3] partitions: Introduce NVIDIA Tegra Partition Table To: Dmitry Osipenko , Stephen Warren , Jens Axboe Cc: Thierry Reding , Jonathan Hunter , =?UTF-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= , David Heidelberg , Peter Geis , Nicolas Chauvet , Adrian Hunter , Billy Laws , linux-tegra , linux-block , Andrey Danin , Gilles Grandou , Ryan Grachek , "linux-mmc@vger.kernel.org" , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 4 Mar 2020 at 18:09, Dmitry Osipenko wrote: > > 04.03.2020 19:36, Ulf Hansson =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > On Tue, 25 Feb 2020 at 01:20, Stephen Warren wr= ote: > >> > >> On 2/24/20 4:18 PM, Dmitry Osipenko wrote: > >>> All NVIDIA Tegra devices use a special partition table format for the > >>> internal storage partitioning. Most of Tegra devices have GPT partiti= on > >>> in addition to TegraPT, but some older Android consumer-grade devices= do > >>> not or GPT is placed in a wrong sector, and thus, the TegraPT is need= ed > >>> in order to support these devices properly in the upstream kernel. Th= is > >>> patch adds support for NVIDIA Tegra Partition Table format that is us= ed > >>> at least by all NVIDIA Tegra20 and Tegra30 devices. > >> > >>> diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.= c > >> > >>> +static void __init tegra_boot_config_table_init(void) > >>> +{ > >>> + void __iomem *bct_base; > >>> + u16 pt_addr, pt_size; > >>> + > >>> + bct_base =3D IO_ADDRESS(TEGRA_IRAM_BASE) + TEGRA_IRAM_BCT_OFFSE= T; > >> > >> This shouldn't be hard-coded. IIRC, the boot ROM writes a BIT (Boot > >> Information Table) to a fixed location in IRAM, and there's some value > >> in the BIT that points to where the BCT is in IRAM. In practice, it > >> might work out that the BCT is always at the same place in IRAM, but > >> this certainly isn't guaranteed. I think there's code in U-Boot which > >> extracts the BCT location from the BIT? Yes, see > >> arch/arm/mach-tegra/ap.c:get_odmdata(). > > > > So, have you considered using the command line partition option, > > rather than adding yet another partition scheme to the kernel? > > > > In principle, you would let the boot loader scan for the partitions, > > likely from machine specific code in U-boot. Then you append these to > > the kernel command line and let block/partitions/cmdline.c scan for > > it. > > The bootloader is usually locked-down on a consumer Tegra machines (it's > signed / encrypted). Right, you are you talking about this from a developer point of view, not from an end product user? I mean, for sure you can upgrade the bootloader on Nvidia products? No, rea= lly? > > Technically, it should be possible to chain-load some custom secondary > bootloader instead of a kernel image, but this is not very practical > because now: > > 1. There is a need to make a custom bootloader and it is quite a lot of > work. > > 2. You'll have to tell everybody that a custom booloader may need to be > used in order to get a working eMMC. Yeah, I get the point. It's not an optimal situation, but I assume it's about informing developers. They can cope with this, no? > > 3. NVIDIA's bootloader already passes a command line parameter to kernel > for locating GPT entry, but this hack is not acceptable for the upstream > kernel. Well, I am just worried that we will end up with one partition format per vendor/product, that wouldn't scale very well. In any case, from mmc point of view I am less concerned, we can find a way to support the needed bits. I just need to review the series more carefully and provide some comments. :-) However, before I do that, I would like to hear Jens opinion about adding a new partition format, so I don't waste my time here. Kind regards Uffe