Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
IronPort-SDR: M4BkTxj10tFmtgKFxchSF6ktnYgtKAoVHNCCIaTus3diu1On3qRcR0RDiwj9lqxvUNx7OX77k1
 Y5U7iqNxQ/NIvGz1s+eVQjP4CL1Le6C1rkOb/lWmRzLM4WL8gYXFlXyrzZLykzcGreRChzt6JE
 A4x/I3cOVjpP8YSgH9Xt1n92w+jQVv68dVoVo/LV6D4Ojbc50OhCxCtU0oWChW7jlN5xP3bvRO
 x+2zqV0wTAsimSihtPyoCsQ7AlfPf0rv1x3NumUf670GFICNlWqkoB6VolYs7mYDUJnx+e9Kuo
 YNY=
From:   Anup Patel <anup.patel@wdc.com>
To:     Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Marc Zyngier <marc.zyngier@arm.com>
Cc:     Atish Patra <atish.patra@wdc.com>,
        Alistair Francis <Alistair.Francis@wdc.com>,
        Anup Patel <anup@brainfault.org>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        Anup Patel <anup.patel@wdc.com>
Subject: [PATCH v4 0/5] New RISC-V Local Interrupt Controller Driver
Date:   Mon,  9 Mar 2020 16:32:06 +0530
Message-Id: <20200309110211.91130-1-anup.patel@wdc.com>
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-MessageSentRepresentingType: 1
Received: from wdc.com (106.51.22.61) by MAXPR01CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2793.11 via Frontend Transport; Mon, 9 Mar 2020 11:02:36 +0000
X-Mailer: git-send-email 2.17.1
X-Originating-IP: [106.51.22.61]
X-MS-PublicTrafficType: Email
X-MS-Office365-Filtering-HT: Tenant
X-MS-Office365-Filtering-Correlation-Id: 139dcd0a-ac2f-4989-d3e7-08d7c419638e
X-MS-TrafficTypeDiagnostic: MN2PR04MB5517:
X-MS-Exchange-Transport-Forked: True
X-Microsoft-Antispam-PRVS: <MN2PR04MB55172C0D98FD53F071FC30748DFE0@MN2PR04MB5517.namprd04.prod.outlook.com>
WDCIPOUTBOUND: EOP-TRUE
X-MS-Oob-TLC-OOBClassifiers: OLM:8273;
X-Forefront-PRVS: 0337AFFE9A
X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10019020)(4636009)(39860400002)(376002)(136003)(396003)(366004)(346002)(189003)(199004)(8886007)(86362001)(26005)(1076003)(55236004)(1006002)(6666004)(5660300002)(44832011)(4326008)(966005)(55016002)(478600001)(36756003)(54906003)(110136005)(81156014)(186003)(8676002)(81166006)(16526019)(7416002)(8936002)(7696005)(316002)(66556008)(956004)(66946007)(66476007)(2616005)(2906002)(52116002)(32040200004);DIR:OUT;SFP:1102;SCL:1;SRVR:MN2PR04MB5517;H:MN2PR04MB6061.namprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1;
X-MS-Exchange-SenderADCheck: 1
X-Microsoft-Antispam: BCL:0;
X-Microsoft-Antispam-Message-Info: +gkPnxeXMtvAI74km+LNuwm/WA5FN9uRYAoC9RXi5vttoqRL5WIAhr21dtu9Mi8Z+i8I6RN40TYhnwdEBT/1s1AYs6r/+8niNwvq+pO3OFpnw9yEAmi4P54CTTy3b0ukJqgDBdeiYj1L6cuf9zpIkp2IRUk86TxiStthXPxmT0pu2NTlzKGbWbLGzE+bdoLVUH36jqsXi+33tqzfXwso5r8bep+75WqzIdzeNt+H0S3RXBnqK4BNElVdreRpXfPeo+QfjapCpTtPv2FYFLhoZdjIQpYHNqm1oa+zc7fb3lw/tJDdrXfT6PpDnzRDtLq2TMLlBEgkywQLx7FEaBkU4RU3xSvOXY3A9SQHiKg6oPxFo/WR9zxbfBdcECuJNWZ5hr8L2NwUw++1K6SywMIF1XqaIjLF7BFyxGXSDckfLNzaL3EoEPSfGO6mYDdZ2uTXeJxsC0gT///catWzjNlQ2vW9QXwhF++4TaMfmZPcCXtfOfjYalUcSDllJ5aBvyPf5dHoqCRpagsnBOxjFOGmFuop++/rs3NpH6nbCPvKlAeG0G8q81oVXTmOOJJG7q1ifN3h7uhUXIsv2ItnHMdGQw==
X-MS-Exchange-AntiSpam-MessageData: uvTnbZiho9UFjB+Z5qkqfgHBX1cc98PhczvC3JDas54XBN09nKfU189UUGVKYhnEStdldxovtIcuOOxM1H4CizTjFAnyaRAkiwLOxIDrsgmU8a80mEHGPIeG1qNEn2ISQkGpT+GQUVuECVXhYUdFug==
X-OriginatorOrg: wdc.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 139dcd0a-ac2f-4989-d3e7-08d7c419638e
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2020 11:02:42.1984
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: 5x2GosQ3B/mYkWiBFomDCMUJmD8YgqsrSFHZMLamd9uoktaV8xv/tO6iPJbD+nNee3VgCaYq19VF95GUWgOeUg==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5517
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

This patchset provides a new RISC-V Local Interrupt Controller Driver
for managing per-CPU local interrupts. The overall approach is inspired
from the way per-CPU local interrupts are handled by Linux ARM64 and
ARM GICv3 driver.

Few advantages of this new driver over previous one are:
1. It registers all local interrupts as per-CPU interrupts
2. The KVM RISC-V can use this driver to implement interrupt
   handler for per-HART guest external interrupt defined by
   the RISC-V H-Extension
3. In future, we can develop drivers for devices with per-HART
   interrupts without changing arch code or this driver

With this patchset, output of "cat /proc/interrupts" looks as follows:
           CPU0       CPU1       CPU2       CPU3       
  2:        379          0          0          0  SiFive PLIC  10  ttyS0
  3:        591          0          0          0  SiFive PLIC   8  virtio0
  5:       5079      10821       8435      12984  RISC-V INTC   5  riscv-timer
IPI0:      2045       2537        891        870  Rescheduling interrupts
IPI1:         9        269         91        168  Function call interrupts
IPI2:         0          0          0          0  CPU stop interrupts

The patchset is based up Linux-5.6-rc5 and can be found at riscv_intc_v4
branch of: https://github.com/avpatel/linux.git

Changes since v3:
 - Rebased to Linux-5.6-rc5 and Atish's PLIC patches
 - Added separate patch to rename and move plic_find_hart_id()
   to arch directory
 - Use riscv_of_parent_hartid() in riscv_intc_init() instead of
   atomic counter

Changes since v2:
 - Dropped PATCH2 since it was merged long-time back
 - Rebased series from Linux-4.19-rc2 to Linux-5.6-rc2

Changes since v1:
 - Removed changes related to puggable IPI triggering
 - Separate patch for self-contained IPI handling routine
 - Removed patch for GENERIC_IRQ kconfig options
 - Added patch to remove do_IRQ() function
 - Rebased upon Atish's SMP patches

Anup Patel (5):
  RISC-V: self-contained IPI handling routine
  RISC-V: Rename and move plic_find_hart_id() to arch directory
  irqchip: RISC-V Per-HART Local Interrupt Controller Driver
  clocksource: timer-riscv: Make timer interrupt as a per-CPU interrupt
  RISC-V: Remove do_IRQ() function

 arch/riscv/Kconfig                 |   1 +
 arch/riscv/include/asm/irq.h       |   5 --
 arch/riscv/include/asm/processor.h |   1 +
 arch/riscv/include/asm/smp.h       |   3 +
 arch/riscv/kernel/cpu.c            |  16 ++++
 arch/riscv/kernel/entry.S          |   4 +-
 arch/riscv/kernel/irq.c            |  33 +------
 arch/riscv/kernel/smp.c            |  11 ++-
 arch/riscv/kernel/traps.c          |   2 -
 drivers/clocksource/timer-riscv.c  |  79 +++++++++++------
 drivers/irqchip/Kconfig            |  13 +++
 drivers/irqchip/Makefile           |   1 +
 drivers/irqchip/irq-riscv-intc.c   | 134 +++++++++++++++++++++++++++++
 drivers/irqchip/irq-sifive-plic.c  |  40 ++++-----
 include/linux/cpuhotplug.h         |   1 +
 15 files changed, 256 insertions(+), 88 deletions(-)
 create mode 100644 drivers/irqchip/irq-riscv-intc.c

-- 
2.17.1