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From:   Peng Fan <peng.fan@nxp.com>
To:     Shawn Guo <shawnguo@kernel.org>
CC:     "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
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        Abel Vesa <abel.vesa@nxp.com>
Subject: RE: [PATCH v2 07/14] clk: imx7ulp: make it easy to change ARM core
 clk
Thread-Topic: [PATCH v2 07/14] clk: imx7ulp: make it easy to change ARM core
 clk
Thread-Index: AQHV5vt/fQalJGbC30maMwignaLHKKhBdxSAgAAAv/A=
Date:   Tue, 10 Mar 2020 06:19:52 +0000
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Hi Shawn,

> Subject: Re: [PATCH v2 07/14] clk: imx7ulp: make it easy to change ARM co=
re
> clk
>=20
> On Wed, Feb 19, 2020 at 03:59:50PM +0800, peng.fan@nxp.com wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > ARM clk could only source from divcore or hsrun_divcore.
> >
> > However when ARM core is running normaly, whether divcore or
> > hwrun_divcore will finally source from SPLL_PFD0. However SPLL_PFD0 is
> > marked with CLK_SET_GATE, so we need to disable SPLL_PFD0, when
> > configure the rate. So add CORE and HSRUN_CORE virtual clk to make it
> > easy to configure the clk using imx_clk_hw_cpu API.
>=20
> It sounds a bit hackish, so would like to hear an ACK from Stephen on it.

Same to i.MX7/8M SoCs, the cpu clk could not change on the fly,
That's why we use a imx_clk_hw_cpu for i.MX7/8M cpu clock.

To i.MX7ULP, it is a bit different, cpu could sources from two clocks
based on a SMC setting which is abstract as a mux in clk-imx7ulp.c.

However we still could not change HSRUN_CORE or CORE clk
on the fly whether the cpu sources form HSRUN_CORE or CORE clk.

That's why I add virtual clk for HSRUN and CORE, same as i.MX7/8M.

Stephen rejected my original patch to use a virtual clk for the final
output which add imx_hw_clk_cpuv2,=20
https://patchwork.kernel.org/patch/11364633/

So I implement the method in this patch which is cleaner and
simple. With this approach, it is easy to reuse cpufreq-dt driver,
we no need a new clk driver and no need a new cpufreq driver
for i.MX7ULP.

Please consider this patch.

Thanks,
Peng.=20


>=20
> Shawn
>=20
> >
> > Since CORE and HSRUN_CORE already marked with CLK_IS_CRITICAL, no
> need
> > to set ARM as CLK_IS_CRITICAL. And when set the rate of ARM clk,
> > prograting it the parent with CLK_SET_RATE_PARENT will finally set the
> > SPLL_PFD0 clk.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  drivers/clk/imx/clk-imx7ulp.c             | 6 ++++--
> >  include/dt-bindings/clock/imx7ulp-clock.h | 5 ++++-
> >  2 files changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx7ulp.c
> > b/drivers/clk/imx/clk-imx7ulp.c index 3710aa0dee9b..634c0b6636b0
> > 100644
> > --- a/drivers/clk/imx/clk-imx7ulp.c
> > +++ b/drivers/clk/imx/clk-imx7ulp.c
> > @@ -29,7 +29,7 @@ static const char * const ddr_sels[]		=3D
> { "apll_pfd_sel", "dummy", "dummy", "dum
> >  static const char * const nic_sels[]		=3D { "firc", "ddr_clk", };
> >  static const char * const periph_plat_sels[]	=3D { "dummy", "nic1_bus_=
clk",
> "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
> >  static const char * const periph_bus_sels[]	=3D { "dummy", "sosc_bus_c=
lk",
> "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_cl=
k", };
> > -static const char * const arm_sels[]		=3D { "divcore", "dummy", "dummy=
",
> "hsrun_divcore", };
> > +static const char * const arm_sels[]		=3D { "core", "dummy", "dummy",
> "hsrun_core", };
> >
> >  /* used by sosc/sirc/firc/ddr/spll/apll dividers */  static const
> > struct clk_div_table ulp_div_table[] =3D { @@ -121,7 +121,9 @@ static
> > void __init imx7ulp_clk_scg1_init(struct device_node *np)
> >  	hws[IMX7ULP_CLK_DDR_SEL]	=3D imx_clk_hw_mux_flags("ddr_sel",
> base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT |
> CLK_OPS_PARENT_ENABLE);
> >
> >  	hws[IMX7ULP_CLK_CORE_DIV]	=3D imx_clk_hw_divider_flags("divcore",
> 	"scs_sel",  base + 0x14, 16, 4, CLK_SET_RATE_PARENT);
> > +	hws[IMX7ULP_CLK_CORE]		=3D imx_clk_hw_cpu("core", "divcore",
> hws[IMX7ULP_CLK_CORE_DIV]->clk, hws[IMX7ULP_CLK_SYS_SEL]->clk,
> hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk);
> >  	hws[IMX7ULP_CLK_HSRUN_CORE_DIV] =3D
> > imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base +
> > 0x1c, 16, 4, CLK_SET_RATE_PARENT);
> > +	hws[IMX7ULP_CLK_HSRUN_CORE] =3D imx_clk_hw_cpu("hsrun_core",
> > +"hsrun_divcore", hws[IMX7ULP_CLK_HSRUN_CORE_DIV]->clk,
> > +hws[IMX7ULP_CLK_HSRUN_SYS_SEL]->clk,
> hws[IMX7ULP_CLK_SPLL_SEL]->clk,
> > +hws[IMX7ULP_CLK_FIRC]->clk);
> >
> >  	hws[IMX7ULP_CLK_DDR_DIV]	=3D imx_clk_hw_divider_gate("ddr_clk",
> "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3,
> >  							       0, ulp_div_table, &imx_ccm_lock);
> @@ -270,7 +272,7 @@
> > static void __init imx7ulp_clk_smc1_init(struct device_node *np)
> >  	base =3D of_iomap(np, 0);
> >  	WARN_ON(!base);
> >
> > -	hws[IMX7ULP_CLK_ARM] =3D imx_clk_hw_mux_flags("arm", base + 0x10,
> 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_IS_CRITICAL);
> > +	hws[IMX7ULP_CLK_ARM] =3D imx_clk_hw_mux_flags("arm", base + 0x10,
> 8,
> > +2, arm_sels, ARRAY_SIZE(arm_sels), CLK_SET_RATE_PARENT);
> >
> >  	imx_check_clk_hws(hws, clk_data->num);
> >
> > diff --git a/include/dt-bindings/clock/imx7ulp-clock.h
> > b/include/dt-bindings/clock/imx7ulp-clock.h
> > index 38145bdcd975..b58370d146e2 100644
> > --- a/include/dt-bindings/clock/imx7ulp-clock.h
> > +++ b/include/dt-bindings/clock/imx7ulp-clock.h
> > @@ -58,7 +58,10 @@
> >  #define IMX7ULP_CLK_HSRUN_SYS_SEL	44
> >  #define IMX7ULP_CLK_HSRUN_CORE_DIV	45
> >
> > -#define IMX7ULP_CLK_SCG1_END		46
> > +#define IMX7ULP_CLK_CORE		46
> > +#define IMX7ULP_CLK_HSRUN_CORE		47
> > +
> > +#define IMX7ULP_CLK_SCG1_END		48
> >
> >  /* PCC2 */
> >  #define IMX7ULP_CLK_DMA1		0
> > --
> > 2.16.4
> >