Received: by 2002:a25:e7d8:0:0:0:0:0 with SMTP id e207csp543500ybh; Tue, 10 Mar 2020 03:48:02 -0700 (PDT) X-Google-Smtp-Source: ADFU+vu9UCZxzadjD1cNIqxzn6OnimzEr/HEs2OHzZ/6k7BdgaDBUtH1/09TD1l9bLyEyClkZS2/ X-Received: by 2002:a9d:64ca:: with SMTP id n10mr16559375otl.325.1583837282136; Tue, 10 Mar 2020 03:48:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1583837282; cv=none; d=google.com; s=arc-20160816; b=vcVR5EnL8OjZzz85vJeBjL4Wl0sZKzwPi6EydLgMrtxw7Q80WupJCV9T7KGgfK6qKo m4UivuYy+/F91UifLHpu79vjcw2ZgHhpnO/udvXlggh3UAR0DW7lq8a+mRY+pt23G5w5 GM7qS3r6Xk+NTGaOjHiYaWboUMt7Ulk7lZIpee+bnHoijYZ9xofMZe96mDACLsmbvoPY FVlE7g3SBx3w0vijwW3Sppe+vzA9ROfUuuur1rcNaicGy7sGOXtgB28x5Usw7Xrzj6mc nwgzOELVRu1eUFTehMEwEdQtyF8sg/eDyZg4UlRUs6H83UIikJT5awYTzHFD3HX1NnG5 uE6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=d0KBZmIYcwPxNsfVx0TVhck5IEUyw6rJghC9iKDBJRI=; b=B/0/TBMFl6tIK17fpP8CFu2+JMFbhLrvUxySEGUCBzXYHY7bPIWsj6qh0tuy2ONS1n XBJokR5rHl5zk4sDIdbZkMOl1T5fKyyGUaA45C/unQZN5dX1V7zv8FY2E6ei5jm2HgG1 0HCHsH75zXIlbqjVoEOLfaIjTEpO7RsLWK572maYwGS2TUbVluWi16+Vok73dedB264g 4i+wPYAeQKkvxm5mtvFtLWQ7mjrPnI7Ox2IvY4eUXsWgeoNiPOng89wYK5VHAI7LinBf Po0qJAdSfLQNQBLg9D8UxEMunl0+BtxvOgcwEmivEqqrRGvokgaC/tJ5WYj5HiZzG7Ba mdqA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g24si8300099otn.296.2020.03.10.03.47.50; Tue, 10 Mar 2020 03:48:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726205AbgCJKrb (ORCPT + 99 others); Tue, 10 Mar 2020 06:47:31 -0400 Received: from mga09.intel.com ([134.134.136.24]:4660 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725937AbgCJKrb (ORCPT ); Tue, 10 Mar 2020 06:47:31 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Mar 2020 03:47:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,518,1574150400"; d="scan'208";a="260743273" Received: from hao-dev.bj.intel.com (HELO localhost) ([10.238.157.65]) by orsmga002.jf.intel.com with ESMTP; 10 Mar 2020 03:47:29 -0700 Date: Tue, 10 Mar 2020 18:26:33 +0800 From: Wu Hao To: Xu Yilun Cc: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, Luwei Kang Subject: Re: [PATCH 2/7] fpga: dfl: pci: add irq info for feature devices enumeration Message-ID: <20200310102633.GB28396@hao-dev> References: <1583749790-10837-1-git-send-email-yilun.xu@intel.com> <1583749790-10837-3-git-send-email-yilun.xu@intel.com> <20200310024626.GB11861@hao-dev> <20200310094143.GB30868@yilunxu-OptiPlex-7050> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200310094143.GB30868@yilunxu-OptiPlex-7050> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 10, 2020 at 05:41:43PM +0800, Xu Yilun wrote: > On Tue, Mar 10, 2020 at 10:46:26AM +0800, Wu Hao wrote: > > Hi Yilun > > > > Some comments inline. : ) > > > > On Mon, Mar 09, 2020 at 06:29:45PM +0800, Xu Yilun wrote: > > > Some DFL FPGA PCIe cards (e.g. Intel FPGA Programmable Acceleration > > > Card) support MSI-X based interrupts. This patch allows PCIe driver > > > to prepare and pass interrupt resources to DFL via enumeration API. > > > These interrupt resources could then be assigned to actual features > > > which use them. > > > > > > Signed-off-by: Luwei Kang > > > Signed-off-by: Wu Hao > > > Signed-off-by: Xu Yilun > > > --- > > > drivers/fpga/dfl-pci.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++---- > > > 1 file changed, 61 insertions(+), 5 deletions(-) > > > > > > diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c > > > index 5387550..a3370e5 100644 > > > --- a/drivers/fpga/dfl-pci.c > > > +++ b/drivers/fpga/dfl-pci.c > > > @@ -80,8 +80,23 @@ static void cci_remove_feature_devs(struct pci_dev *pcidev) > > > dfl_fpga_feature_devs_remove(drvdata->cdev); > > > } > > > > > > +static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec) > > > +{ > > > + int *table, i; > > > + > > > + table = kcalloc(nvec, sizeof(int), GFP_KERNEL); > > > > Maybe devm_ version is better? > > This table will be freed right after dfl_fpga_enum_info_add_irq(). Maybe > don't need devm_ version. > > > > > > + if (!table) > > > + return NULL; > > > + > > > + for (i = 0; i < nvec; i++) > > > > i should be unsigned int as well? > > Yes I should change it. > > > > > > + table[i] = pci_irq_vector(pcidev, i); Hi Yilun, one more place here. table = kcalloc(nevc, sizeof(int), GFP_KERNEL); if (table) { ... } return table; Thanks Hao > > > + > > > + return table; > > > +} > > > + > > > /* enumerate feature devices under pci device */ > > > -static int cci_enumerate_feature_devs(struct pci_dev *pcidev) > > > +static int cci_enumerate_feature_devs(struct pci_dev *pcidev, > > > + unsigned int nvec) > > > { > > > struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); > > > struct dfl_fpga_enum_info *info; > > > @@ -89,6 +104,7 @@ static int cci_enumerate_feature_devs(struct pci_dev *pcidev) > > > resource_size_t start, len; > > > int port_num, bar, i, ret = 0; > > > void __iomem *base; > > > + int *irq_table; > > > u32 offset; > > > u64 v; > > > > > > @@ -97,6 +113,18 @@ static int cci_enumerate_feature_devs(struct pci_dev *pcidev) > > > if (!info) > > > return -ENOMEM; > > > > > > + /* add irq info for enumeration if really needed */ > > > + if (nvec) { > > > + irq_table = cci_pci_create_irq_table(pcidev, nvec); > > > + if (irq_table) { > > > + dfl_fpga_enum_info_add_irq(info, nvec, irq_table); > > > + kfree(irq_table); > > > + } else { > > > + ret = -ENOMEM; > > > + goto enum_info_free_exit; > > > + } > > > + } > > > + > > > /* start to find Device Feature List from Bar 0 */ > > > base = cci_pci_ioremap_bar(pcidev, 0); > > > if (!base) { > > > @@ -173,6 +201,28 @@ static int cci_enumerate_feature_devs(struct pci_dev *pcidev) > > > return ret; > > > } > > > > > > +static int cci_pci_alloc_irq(struct pci_dev *pcidev) > > > +{ > > > + int nvec = pci_msix_vec_count(pcidev); > > > + int ret; > > > + > > > + if (nvec <= 0) { > > > + dev_dbg(&pcidev->dev, "fpga interrupt not supported\n"); > > > + return 0; > > > + } > > > + > > > + ret = pci_alloc_irq_vectors(pcidev, nvec, nvec, PCI_IRQ_MSIX); > > > + if (ret < 0) > > > + return ret; > > > + > > > + return nvec; > > > +} > > > + > > > +static void cci_pci_free_irq(struct pci_dev *pcidev) > > > +{ > > > + pci_free_irq_vectors(pcidev); > > > +} > > > + > > > static > > > int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid) > > > { > > > @@ -210,14 +260,19 @@ int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid) > > > goto disable_error_report_exit; > > > } > > > > > > - ret = cci_enumerate_feature_devs(pcidev); > > > - if (ret) { > > > - dev_err(&pcidev->dev, "enumeration failure %d.\n", ret); > > > + ret = cci_pci_alloc_irq(pcidev); > > > + if (ret < 0) { > > > + dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", ret); > > > > we prepare mmio resources in side cci_enumerate_feature_devs. > > > > maybe we could put irq resources code in side cce_enumerate_feature_devs too? > > Yes I will try to change it in patch v2. > > Thanks for your quick response. > > > > > > > Thanks > > Hao > > > > > goto disable_error_report_exit; > > > } > > > > > > - return ret; > > > + ret = cci_enumerate_feature_devs(pcidev, (unsigned int)ret); > > > + if (!ret) > > > + return ret; > > > + > > > + dev_err(&pcidev->dev, "enumeration failure %d.\n", ret); > > > > > > + cci_pci_free_irq(pcidev); > > > disable_error_report_exit: > > > pci_disable_pcie_error_reporting(pcidev); > > > return ret; > > > @@ -263,6 +318,7 @@ static void cci_pci_remove(struct pci_dev *pcidev) > > > cci_pci_sriov_configure(pcidev, 0); > > > > > > cci_remove_feature_devs(pcidev); > > > + cci_pci_free_irq(pcidev); > > > pci_disable_pcie_error_reporting(pcidev); > > > } > > > > > > -- > > > 2.7.4