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Tue, 10 Mar 2020 23:03:33 -0700 (PDT) Received: from localhost ([122.171.122.128]) by smtp.gmail.com with ESMTPSA id x72sm11377214pfc.156.2020.03.10.23.03.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 Mar 2020 23:03:32 -0700 (PDT) Date: Wed, 11 Mar 2020 11:33:30 +0530 From: Viresh Kumar To: Anson Huang Cc: rjw@rjwysocki.net, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, abel.vesa@nxp.com, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linux-imx@nxp.com Subject: Re: [PATCH] cpufreq: imx-cpufreq-dt: Correct i.MX8MP's market segment fuse location Message-ID: <20200311060330.ecvdlvflahdbptsi@vireshk-i7> References: <1583819296-7763-1-git-send-email-Anson.Huang@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1583819296-7763-1-git-send-email-Anson.Huang@nxp.com> User-Agent: NeoMutt/20180716-391-311a52 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10-03-20, 13:48, Anson Huang wrote: > i.MX8MP's market segment fuse field is bit[6:5], correct it. > > Fixes: 83fe39ad0a48 ("cpufreq: imx-cpufreq-dt: Add i.MX8MP support") > Signed-off-by: Anson Huang > --- > drivers/cpufreq/imx-cpufreq-dt.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/cpufreq/imx-cpufreq-dt.c b/drivers/cpufreq/imx-cpufreq-dt.c > index 0e29d88..de206d2 100644 > --- a/drivers/cpufreq/imx-cpufreq-dt.c > +++ b/drivers/cpufreq/imx-cpufreq-dt.c > @@ -19,6 +19,8 @@ > #define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8) > #define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6 > #define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6) > +#define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT 5 > +#define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 5) > > /* cpufreq-dt device registered by imx-cpufreq-dt */ > static struct platform_device *cpufreq_dt_pdev; > @@ -45,7 +47,13 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev) > else > speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK) > >> OCOTP_CFG3_SPEED_GRADE_SHIFT; > - mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT; > + > + if (of_machine_is_compatible("fsl,imx8mp")) > + mkt_segment = (cell_value & IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK) > + >> IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT; > + else > + mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) > + >> OCOTP_CFG3_MKT_SEGMENT_SHIFT; > > /* > * Early samples without fuses written report "0 0" which may NOT > -- Applied. Thanks. -- viresh