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Date:   Wed, 11 Mar 2020 10:18:15 +0100
From:   Robert Richter <rrichter@marvell.com>
To:     Marc Zyngier <maz@kernel.org>
CC:     <kvmarm@lists.cs.columbia.edu>, <linux-kernel@vger.kernel.org>,
        Eric Auger <eric.auger@redhat.com>,
        James Morse <james.morse@arm.com>,
        Julien Thierry <julien.thierry.kdev@gmail.com>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Andrew Murray <Andrew.Murray@arm.com>,
        Zenghui Yu <yuzenghui@huawei.com>
Subject: Re: [PATCH v3 03/32] irqchip/gic-v3: Workaround Cavium TX1 erratum
 when reading GICD_TYPER2
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References: <20191224111055.11836-1-maz@kernel.org>
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On 11.03.20 09:03:48, Marc Zyngier wrote:
> Hi Robert,
> 
> On 2020-03-11 08:45, Robert Richter wrote:
> > Hi Marc,
> > 
> > On 10.03.20 11:41:09, Marc Zyngier wrote:
> > > On 2020-03-09 22:11, Robert Richter wrote:
> > > > On 24.12.19 11:10:26, Marc Zyngier wrote:
> > 
> > > > > @@ -1502,6 +1512,12 @@ static const struct gic_quirk gic_quirks[] = {
> > > > >  		.mask	= 0xffffffff,
> > > > >  		.init	= gic_enable_quirk_hip06_07,
> > > > >  	},
> > > > > +	{
> > > > > +		.desc	= "GICv3: Cavium TX1 GICD_TYPER2 erratum",
> > > >
> > > > There is no errata number yet.
> > > 
> > > Please let me know when/if you obtain one.
> > 
> > GIC-38539: GIC faults when accessing reserved GICD_TYPER2 register
> > 
> > Applies to (covered with iidr mask below):
> > 
> >  ThunderX: CN88xx
> >  OCTEON TX: CN83xx, CN81xx
> >  OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
> > 
> > Issue: Access to GIC reserved registers results in an exception.
> > Notes:
> > 1) This applies to other reserved registers too.
> > 2) The errata number is unique over all IP blocks, so a macro
> >    CAVIUM_ERRATUM_38539 is ok.
> 
> Great, thanks a lot for chasing this. One question though: does this
> apply to the distributor only? Or to all reserved registers regardless
> of the architectural block they are in?

It is the whole GIC IP block covered by GICv3 spec. It was implemented
during a very early state of the spec and the RES0 requirement was
added later to reserved registers. CN8xxx GIC CSR access checking is
stricter implemented, so if no register is present, an access results
in a fault other than simply returning a RAZ/WI.

Thanks,

-Robert

> 
> It won't change the workaround for now, but knowing the scope of the
> erratum will help future developments.
> 
> Thanks,
> 
>         M.
> -- 
> Jazz is not dead. It just smells funny...