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Date:   Wed, 11 Mar 2020 08:23:47 -0700
From:   Tony Lindgren <tony@atomide.com>
To:     Roger Quadros <rogerq@ti.com>
Cc:     Tero Kristo <t-kristo@ti.com>, hch@lst.de, robin.murphy@arm.com,
        robh+dt@kernel.org, nm@ti.com, nsekhar@ti.com,
        linux-omap@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ARM: dts: dra7: Add bus_dma_limit for L3 bus
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* Roger Quadros <rogerq@ti.com> [200311 07:21]:
> 
> 
> On 10/03/2020 17:48, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [200310 14:46]:
> > > On 10/03/2020 13:53, Roger Quadros wrote:
> > > > The L3 interconnect can access only 32-bits of address.
> > > > Add the dma-ranges property to reflect this limit.
> > > > 
> > > > This will ensure that no device under L3 is
> > > > given > 32-bit address for DMA.
> > > > 
> > > > Issue was observed only with SATA on DRA7-EVM with 4GB RAM
> > > > and CONFIG_ARM_LPAE enabled. This is because the controller
> > > > can perform 64-bit DMA and was setting the dma_mask to 64-bit.
> > > > 
> > > > Setting the correct bus_dma_limit fixes the issue.
> > > 
> > > This seems kind of messy to modify almost every DT node because of this....
> > > Are you sure this is the only way to get it done? No way to modify the sata
> > > node only which is impacted somehow?
> > > 
> > > Also, what if you just pass 0xffffffff to the dma-ranges property? That
> > > would avoid modifying every node I guess.
> > 
> > Also, I think these interconnects are not limited to 32-bit access.
> 
> But from Table 2-1. L3_MAIN Memory Map
> 
> Start address	0x0000_0000
> End address	0xFFFF_FFFF
> 
> So it is 32-bit limit, right?

Hmm so what war Robin saying earlier that DMA access seems to be
limited to lower 2GB only though?

Regards,

Tony