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[209.132.180.67]) by mx.google.com with ESMTP id l19si1207369oii.54.2020.03.11.08.51.30; Wed, 11 Mar 2020 08:51:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730087AbgCKPtf convert rfc822-to-8bit (ORCPT + 99 others); Wed, 11 Mar 2020 11:49:35 -0400 Received: from relay2-d.mail.gandi.net ([217.70.183.194]:39541 "EHLO relay2-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729921AbgCKPtf (ORCPT ); Wed, 11 Mar 2020 11:49:35 -0400 X-Originating-IP: 90.89.41.158 Received: from xps13 (lfbn-tou-1-1473-158.w90-89.abo.wanadoo.fr [90.89.41.158]) (Authenticated sender: miquel.raynal@bootlin.com) by relay2-d.mail.gandi.net (Postfix) with ESMTPSA id 502E640008; Wed, 11 Mar 2020 15:49:33 +0000 (UTC) Date: Wed, 11 Mar 2020 16:49:32 +0100 From: Miquel Raynal To: shiva.linuxworks@gmail.com Cc: Boris Brezillon , Richard Weinberger , Vignesh Raghavendra , Frieder Schrempf , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Shivamurthy Shastri Subject: Re: [PATCH v6 0/6] Add new series Micron SPI NAND devices Message-ID: <20200311164932.23cc7a42@xps13> In-Reply-To: <20200309115230.7207-1-sshivamurthy@micron.com> References: <20200309115230.7207-1-sshivamurthy@micron.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Shiva, shiva.linuxworks@gmail.com wrote on Mon, 9 Mar 2020 12:52:24 +0100: > From: Shivamurthy Shastri > > This patchset is for the new series of Micron SPI NAND devices, and the > following links are their datasheets. > > M78A: > [1] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf > [2] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdf > > M79A: > [3] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf > [4] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdf > > M70A: > [5] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf > [6] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf > [7] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf > [8] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdf > > Changes since v5: > ----------------- > > 1. Rebased series to v5.6-rc1. I am very sorry but actually I had issues applying all your patches not because they were not based on v5.6-rc1, but because since then I applied a patch changing the detection that changed the content of a lot of structures (including in Micron's patches). Can you please rebase again on top of the current nand/next? I am very sorry for this extra work, this is my mistake. Head should be: a5d53ad26a8b ("mtd: rawnand: brcmnand: Add support for flash-edu for dma transfers") And the culprit commit is: f1541773af49 ("mtd: spinand: rework detect procedure for different READ_ID operation") Thanks, Miquèl