Received: by 2002:a25:e7d8:0:0:0:0:0 with SMTP id e207csp362448ybh; Thu, 12 Mar 2020 03:29:48 -0700 (PDT) X-Google-Smtp-Source: ADFU+vvJp2pzKLFluuLSUjfya0CVLcrRlHL1/Zq7D7I9pYETAbz7yGBKpVjq0nKAZxIhxxpkU45m X-Received: by 2002:a05:6808:3b3:: with SMTP id n19mr2099353oie.114.1584008988164; Thu, 12 Mar 2020 03:29:48 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1584008988; cv=pass; d=google.com; s=arc-20160816; b=DRsvcqkJor9HWeahQXH6aX6dLc3DQ+r1bNIaEGXVe1uoTFGHMyYxGWGIMk/IniRHxF lnrESB4VfrmkgRla7nvSci0nVPBkB57PxVoKWUxFNxWSoQe54J4QxIkzKed/sX9WdpEk RbnG1QvPs7F904U67OPX6+mrnW69LWEVpjIM9RJsFcyaZSW9WRn2T4Hs2V2icyWQWSmh blAWKwICZdEP0UcqhndznyiS/SBdjlV9tIqgU/r8e8vJh175ssVsIkt+WaB+1OfqtVOP yKJOnsUIWeO45J1bf69iQfhU+d1+FwGFVxH81EVFpX5Y1W/Ib+Ccat/tibMfzDd0XbFx mAcw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=9HxmGmzMPjDdcdVa4OtZe36wcPfY0iU6dXF19EHCpHw=; b=trpAmwnZzagqQDYl4HKmhL8dk4YE4IoaOZJ/FnYau5vgpT/K0fPPQyvGiM0GJXJkX1 2s5UjO97A18bhLXRKZ89rJ6y/VN/YWX51n0rey6GsHM0NK3xQKDRR8FabQXaM7a8V4vy +b8Zs5zxqe7NjTs2K4nwR7ks8b37WeU/lYs5tVhkscb/bco++P4IWJp4k+0pnMIcxHML A2uBOlQ5lo+HCX8SZ17shW3ML/MHK0pOHM+R3R2yQJnnNLdhM/7gkgAbfIdD6xtEhSiH VERZ2nT4Dpl9+7M/6qXe/SYE14EZqQgoOmftE3QZUQYlbxRVue6FKZioUrgGd93wZRXN QNuw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=UmBsv8Oz; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t22si2391256oth.211.2020.03.12.03.29.36; Thu, 12 Mar 2020 03:29:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=UmBsv8Oz; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726558AbgCLK16 (ORCPT + 99 others); Thu, 12 Mar 2020 06:27:58 -0400 Received: from mail-eopbgr60061.outbound.protection.outlook.com ([40.107.6.61]:27203 "EHLO EUR04-DB3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726841AbgCLK15 (ORCPT ); Thu, 12 Mar 2020 06:27:57 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=btLWv/ygnPzyb0XMx0ZsPrdgj8UuW+1bMNf2K+oHzdCfSbBZsLb55wlgJ4N/m7k7nZk3ESkt722uuQyjViQ08nSRnx0LQbyy8CKZWFmbQ8lw+gRoKxwE2aVDezLhDAfoSmXECp4yWtAMsM6K7J3Wot7HYbtFxb69YH2p7KofVb6xNkRYKWyqZYCHcDTu9MIQak5akN59AEWh4400gesbsL/ZiRSTAZ7r1UsTMePL9d5Sdss3R2t0fOmSoSqs1yOc+XlA2O/9Eb/0EfZuP+xmZI1OPJBQ2WFcvXwNHtdZqbR+p/y6ihDGor77phbjHPh6hmovkbC9wzNiNOVHUp4y9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9HxmGmzMPjDdcdVa4OtZe36wcPfY0iU6dXF19EHCpHw=; b=DS5A1h/FywI8AkCaTnV1ybrpjOXmFSmgEbi5tCOPijw74AQtW6wmidnuQUMFsF/aoSgNnD54asOu4Xy9K/pQd7K04raa9KoJ7wseFX7oMkl/TfpPB3RkHmhYtXFSfB5K6cLcDM61tbq6gwcHRuwwjTL2ZNY6h7e6/elmbbr0WS4Da3cOwDYKF+m0mGMuf+9uYttGiLRJrpg9+ufxrKjqZdILzbWNbxRyieV+BxplSarxgICpZLrzeowIhPLYzUmyrrg4ZK1BsvUzgHBJjNTR6xtuzBrQuY43TsccRf9He45BsbzD9qTTK5cEvuSExIoV9UCNRcgeIfWH7VLqvF3myA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9HxmGmzMPjDdcdVa4OtZe36wcPfY0iU6dXF19EHCpHw=; b=UmBsv8OzuEP4TcM8LhNQ2t2cGehavCOIy/wmjb0bR2eHkWSFJdEguVo/fExPaPtRrszjn9+qfhFuE3zH2WKLSNPfq8HzelozVMD1f2IDRTn3b6ck3Ci5a+Q2OFuIPTPCMifx2dWNJR8i62les3+n+c27MU9MJPVIYAMiyEyfXXY= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; Received: from AM0PR04MB4481.eurprd04.prod.outlook.com (52.135.147.15) by AM0PR04MB4195.eurprd04.prod.outlook.com (52.134.92.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2814.14; Thu, 12 Mar 2020 10:26:58 +0000 Received: from AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::548f:4941:d4eb:4c11]) by AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::548f:4941:d4eb:4c11%6]) with mapi id 15.20.2793.018; Thu, 12 Mar 2020 10:26:58 +0000 From: peng.fan@nxp.com To: shawnguo@kernel.org, s.hauer@pengutronix.de, leonard.crestez@nxp.com, sboyd@kernel.org, abel.vesa@nxp.com Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Anson.Huang@nxp.com, daniel.baluta@nxp.com, aford173@gmail.com, ping.bai@nxp.com, jun.li@nxp.com, l.stach@pengutronix.de, andrew.smirnov@gmail.com, agx@sigxcpu.org, angus@akkea.ca, heiko@sntech.de, fugang.duan@nxp.com, linux-clk@vger.kernel.org, Peng Fan Subject: [PATCH V2 04/10] clk: imx8mp: Define gates for pll1/2 fixed dividers Date: Thu, 12 Mar 2020 18:19:38 +0800 Message-Id: <1584008384-11578-5-git-send-email-peng.fan@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584008384-11578-1-git-send-email-peng.fan@nxp.com> References: <1584008384-11578-1-git-send-email-peng.fan@nxp.com> Content-Type: text/plain X-ClientProxiedBy: SG2PR03CA0113.apcprd03.prod.outlook.com (2603:1096:4:91::17) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR03CA0113.apcprd03.prod.outlook.com (2603:1096:4:91::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2835.7 via Frontend Transport; Thu, 12 Mar 2020 10:26:51 +0000 X-Mailer: git-send-email 2.7.4 X-Originating-IP: [119.31.174.66] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: d6c5198f-4fcc-42ad-735b-08d7c66fe4bc X-MS-TrafficTypeDiagnostic: AM0PR04MB4195:|AM0PR04MB4195: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:576; X-Forefront-PRVS: 0340850FCD X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(136003)(366004)(39860400002)(346002)(376002)(396003)(199004)(956004)(26005)(6512007)(9686003)(2616005)(86362001)(8676002)(186003)(6506007)(81166006)(6666004)(8936002)(7416002)(6486002)(478600001)(52116002)(69590400007)(316002)(66946007)(66476007)(16526019)(5660300002)(66556008)(36756003)(81156014)(4326008)(2906002)(32563001);DIR:OUT;SFP:1101;SCL:1;SRVR:AM0PR04MB4195;H:AM0PR04MB4481.eurprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /v9wVAGfxu4wuBgWfein2vG6SO8weDMNRpywWbILIE6nSt7LzyjjY8h5WUzTNYqJXCXtaWe/lR15/kWBw7WALH9L+s5yKRWSfhh0htsYS+IbInwYPWi4xcDORwzQWp4YfiC6HV5nx0q1/+vbp/Odzflrzzxu8K7dmIfQgGZabXGSioQnrJQzK+lqD7cW5nbAqnGCG4gl/fdmTPR16iJSu8RIdP/+iNYQGgW2CHifIi6ZxpgumjkjjnRJW8MOjOXHvKAtLlCIHgVw7yaZP34AJVYRfPf22nFINaXCi2Qn/QsRAB5OGzTrBcIPTCHmpG8xylkF7V20bP54NNg2785kSLRyJ0XNRT/toUm71gkVRYNSUgpWrAiTgLjX2hKCjv1dCqRJ5FFYUjb8EP8pCXJ8NNzta2pWlAd+ivN5D6W0Hqaipn94jBY7WfUc7rkgeSetHp3mJ7naKi3xejvpO0NX4rEjNazE6EzNpG++52QvuK+/S5+QiOT8btdp33uQX+GhpIt+FbHwdyTV+SjHx1L+mg== X-MS-Exchange-AntiSpam-MessageData: ELQNFiQMZgeaMzqu5WJaB3GWHLDDZCqdxa6e+JSM7ujgm6PorTMh3y5OlsVdzpUWKptzZIbkls/kpgU7WTJOUQGWodgLBP6Nk4CFSRu09xiIl+UvZhLUn63zK8g7zYBXfTvExaS3VbzTSOd8JvQ+ww== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d6c5198f-4fcc-42ad-735b-08d7c66fe4bc X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2020 10:26:57.9888 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: D8iF4b2mFiqf/OsVu8vZNmuCl1EQmxboXSRDXMWWOc6uP23vg02l237Xgl+ooozD3JE688VmonKA2NeSmUd6cA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4195 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Peng Fan Inspried from commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers") On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate. Only one of these gates (the one "dividing" by one) is currently defined and it's incorrectly set as the parent of all the fixed-factor dividers. Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed dividers. Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8mp.c | 54 +++++++++++++++++++++----------- include/dt-bindings/clock/imx8mp-clock.h | 19 ++++++++++- 2 files changed, 54 insertions(+), 19 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index e9ed8a188031..a7613c7355c8 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -504,28 +504,46 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", anatop_base + 0x64, 11); hws[IMX8MP_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", anatop_base + 0x74, 11); hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11); - hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11); - hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11); hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11); - hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); - hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); - hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); - hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); - hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); - hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); - hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); - hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + hws[IMX8MP_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1_bypass", anatop_base + 0x94, 27); + hws[IMX8MP_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1_bypass", anatop_base + 0x94, 25); + hws[IMX8MP_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1_bypass", anatop_base + 0x94, 23); + hws[IMX8MP_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1_bypass", anatop_base + 0x94, 21); + hws[IMX8MP_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1_bypass", anatop_base + 0x94, 19); + hws[IMX8MP_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1_bypass", anatop_base + 0x94, 17); + hws[IMX8MP_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1_bypass", anatop_base + 0x94, 15); + hws[IMX8MP_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1_bypass", anatop_base + 0x94, 13); + hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11); + + hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20); + hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10); + hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8); + hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6); + hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5); + hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4); + hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3); + hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2); hws[IMX8MP_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); - hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); - hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); - hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); - hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); - hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); - hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); - hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); - hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + hws[IMX8MP_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2_bypass", anatop_base + 0x104, 27); + hws[IMX8MP_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2_bypass", anatop_base + 0x104, 25); + hws[IMX8MP_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2_bypass", anatop_base + 0x104, 23); + hws[IMX8MP_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2_bypass", anatop_base + 0x104, 21); + hws[IMX8MP_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2_bypass", anatop_base + 0x104, 19); + hws[IMX8MP_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2_bypass", anatop_base + 0x104, 17); + hws[IMX8MP_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2_bypass", anatop_base + 0x104, 15); + hws[IMX8MP_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2_bypass", anatop_base + 0x104, 13); + hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11); + + hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20); + hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10); + hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8); + hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6); + hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5); + hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4); + hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3); + hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2); hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); hws[IMX8MP_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", ccm_base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)); diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 47ab082238b4..46c69cd66c62 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -296,6 +296,23 @@ #define IMX8MP_CLK_ARM 287 #define IMX8MP_CLK_A53_CORE 288 -#define IMX8MP_CLK_END 289 +#define IMX8MP_SYS_PLL1_40M_CG 289 +#define IMX8MP_SYS_PLL1_80M_CG 290 +#define IMX8MP_SYS_PLL1_100M_CG 291 +#define IMX8MP_SYS_PLL1_133M_CG 292 +#define IMX8MP_SYS_PLL1_160M_CG 293 +#define IMX8MP_SYS_PLL1_200M_CG 294 +#define IMX8MP_SYS_PLL1_266M_CG 295 +#define IMX8MP_SYS_PLL1_400M_CG 296 +#define IMX8MP_SYS_PLL2_50M_CG 297 +#define IMX8MP_SYS_PLL2_100M_CG 298 +#define IMX8MP_SYS_PLL2_125M_CG 299 +#define IMX8MP_SYS_PLL2_166M_CG 300 +#define IMX8MP_SYS_PLL2_200M_CG 301 +#define IMX8MP_SYS_PLL2_250M_CG 302 +#define IMX8MP_SYS_PLL2_333M_CG 303 +#define IMX8MP_SYS_PLL2_500M_CG 304 + +#define IMX8MP_CLK_END 305 #endif -- 2.16.4