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[73.241.114.122]) by smtp.gmail.com with ESMTPSA id 15sm49441428pfp.125.2020.03.12.07.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 07:21:28 -0700 (PDT) Date: Thu, 12 Mar 2020 07:21:26 -0700 From: Richard Cochran To: Lokesh Vutla Cc: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Thierry Reding , Tony Lindgren , Linux OMAP Mailing List , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Sekhar Nori , Vignesh R , kernel@pengutronix.de Subject: Re: [PATCH v3 4/5] pwm: omap-dmtimer: Do not disable pwm before changing period/duty_cycle Message-ID: <20200312142126.GB2466@localhost> References: <20200312042210.17344-1-lokeshvutla@ti.com> <20200312042210.17344-5-lokeshvutla@ti.com> <20200312064042.p7himm3odxjyzroi@pengutronix.de> <20200312084739.isixgdo3txr6rjzg@pengutronix.de> <2a5a06cd-7aca-c450-b048-33329d058eca@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2a5a06cd-7aca-c450-b048-33329d058eca@ti.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 12, 2020 at 04:14:34PM +0530, Lokesh Vutla wrote: > But the problem here is that inactive breaks between two periods is not desired. > Because the pwm is used to generate a 1PPS signal and is continuously > synchronized with PTP clock. The 1-PPS case is the "easy" one. If the PWM is adjustable on the fly, then people will use it with higher frequency signals. > I am up if this can be solved generically. But updating period is very specific > to hardware implementation. Not sure what generic solution can be brought out of > this. Please correct me if I am wrong. What happens today when the PWM frequency or duty cycle are changed while the signal is enabled? Do different PWM devices/drivers behave the same way? Does this series change the behavior of the am335x and friends? Thanks, Richard