Received: by 2002:a25:e7d8:0:0:0:0:0 with SMTP id e207csp643981ybh; Thu, 12 Mar 2020 08:30:05 -0700 (PDT) X-Google-Smtp-Source: ADFU+vvEjQUzSW85gYIBU4jyyek2+rWB7Tuf34Ts27HS1c19AqZZt/BZO7XZEwrvJUxRaNK06bGm X-Received: by 2002:a05:6808:14d:: with SMTP id h13mr3102179oie.121.1584027005318; Thu, 12 Mar 2020 08:30:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1584027005; cv=none; d=google.com; s=arc-20160816; b=zopBsxkL1lR2PmSQirmQIECi95jKfeeegN5sC3qCdP7uIwcKDVYa4OPKIfpMJyrQe5 2NK9rezCHKZDdSlK3Ojpv5ideajXi0B82rylbCWf9QpAhXAQG9kWE14jTUXTFInXtbRV SSzZ05DV39EKjQhcwCSgbLbAiEPw7owwu56qpRr6g2pxvIy4JGSBaldOLRyuRt50ylJF /Zzh5EBN2jj9Sh92Agk6IoP6yOl1CyXBXGfTqGdWO1EgeM9Xaw88nSWbxEgjmgHE+Xlw BFZibSAO/wxgTsB8PqEMrBv6s0RXnNduKHhj7veOy9uNiY/IUgNWZ8lmbeM5Vx+qIfFG +EdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:content-language :content-transfer-encoding:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject; bh=20CmxRXQV14NK/AWzN5cjVv0G+jcfKKJHsLGW1THEX0=; b=K5oszB8oBX3gHSSumNaqI0VWGs/CtpRh/nyPvYipg2WU/DlOvg6zgvwNenZZIZcXrE N63x7QJyLltR5YWL4wcfiHZPPvjWzrjdNwQHT4oWUNUFBY3TJVxcf/BDX3ad27eu6YBZ +jGLlm+TdYBZpceSCr2gQ0NKsuvdFdWDJf3x1kpb901F967ZnsUdKQpDypiyFnLORfxv dAYupwmNKNrtA5un0bm9CEA/Cc1CIK6/Ae6nXykQNQ3HVF4dQu8yz/vw1e2eCVlyseOr O1l9Ma9CEem9fuiyJNm9BCTQ5sxRbBzfD8gfLaEBCSgwsxX+7aI8OUjZKzL16+7+CMaz dSQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=ADovG4BR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b21si3157195otp.79.2020.03.12.08.29.52; Thu, 12 Mar 2020 08:30:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=ADovG4BR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727867AbgCLP2h (ORCPT + 99 others); Thu, 12 Mar 2020 11:28:37 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:7878 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727455AbgCLP2g (ORCPT ); Thu, 12 Mar 2020 11:28:36 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 12 Mar 2020 08:27:03 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 12 Mar 2020 08:28:35 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 12 Mar 2020 08:28:35 -0700 Received: from [10.2.172.79] (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 12 Mar 2020 15:28:35 +0000 Subject: Re: [PATCH v2 1/2] sdhci: tegra: Implement Tegra specific set_timeout callback To: Ulf Hansson CC: Adrian Hunter , Bradley Bolen , Thierry Reding , "Jon Hunter" , Aniruddha Tvs Rao , linux-tegra , Linux Kernel Mailing List , "linux-mmc@vger.kernel.org" References: <1583886030-11339-1-git-send-email-skomatineni@nvidia.com> From: Sowjanya Komatineni Message-ID: <7bf5bfb5-b07c-96d3-2c33-124085a36a65@nvidia.com> Date: Thu, 12 Mar 2020 08:28:40 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584026823; bh=20CmxRXQV14NK/AWzN5cjVv0G+jcfKKJHsLGW1THEX0=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Transfer-Encoding: Content-Language; b=ADovG4BRKRpq/sgIlNDARFZ4ko1wfbqEB9VeDNZfevPxfK2VbKtn29YaHthii6+Un XjYDb9qBqjmsO2Fa9DrOQYUn8NmKv1QqYZ/xREDcSA8Y1vUem9PwNTJosMSX7082CL KryHBytg59ESxmiBhIY9XVI8V7MwiAu8eLFFD2Sov3efJEdp+Ji93cyS63BFnwm4P/ 7BPumYrK6nha3M/Gk6HmAj4hckZzXRuSywOFvVRIeFWhva0UZLXPQ+1nSUSQvrV53p ehmkoyigZ99w7cgnS8f1/Y9/ZD8TKa0du2G1QhJ8ZdmAQ95bz85JTxIT2xH+BoaZqg rWTMAc57K3zXQ== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/12/20 6:08 AM, Ulf Hansson wrote: > External email: Use caution opening links or attachments > > > -trimmed cc list > > On Thu, 12 Mar 2020 at 00:51, Sowjanya Komatineni > wrote: >> Tegra host supports HW busy detection and timeouts based on the >> count programmed in SDHCI_TIMEOUT_CONTROL register and max busy >> timeout it supports is 11s in finite busy wait mode. >> >> Some operations like SLEEP_AWAKE, ERASE and flush cache through >> SWITCH commands take longer than 11s and Tegra host supports >> infinite HW busy wait mode where HW waits forever till the card >> is busy without HW timeout. >> >> This patch implements Tegra specific set_timeout sdhci_ops to allow >> switching between finite and infinite HW busy detection wait modes >> based on the device command expected operation time. >> >> Signed-off-by: Sowjanya Komatineni > Applied for next, thanks! > > We should probably tag this for stable as well, don't you think? > > Kind regards > Uffe Yes, we need this for stable as well. As this is applied for next, looks like can't re-send patch with tag. Can you please help to add tag if you don't mind? > > >> --- >> drivers/mmc/host/sdhci-tegra.c | 31 +++++++++++++++++++++++++++++++ >> 1 file changed, 31 insertions(+) >> >> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c >> index a25c3a4..fa8f6a4 100644 >> --- a/drivers/mmc/host/sdhci-tegra.c >> +++ b/drivers/mmc/host/sdhci-tegra.c >> @@ -45,6 +45,7 @@ >> #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 >> >> #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 >> +#define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT BIT(0) >> #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 >> #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 >> #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 >> @@ -1227,6 +1228,34 @@ static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask) >> return 0; >> } >> >> +static void tegra_sdhci_set_timeout(struct sdhci_host *host, >> + struct mmc_command *cmd) >> +{ >> + u32 val; >> + >> + /* >> + * HW busy detection timeout is based on programmed data timeout >> + * counter and maximum supported timeout is 11s which may not be >> + * enough for long operations like cache flush, sleep awake, erase. >> + * >> + * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows >> + * host controller to wait for busy state until the card is busy >> + * without HW timeout. >> + * >> + * So, use infinite busy wait mode for operations that may take >> + * more than maximum HW busy timeout of 11s otherwise use finite >> + * busy wait mode. >> + */ >> + val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); >> + if (cmd && cmd->busy_timeout >= 11 * HZ) >> + val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; >> + else >> + val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; >> + sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL); >> + >> + __sdhci_set_timeout(host, cmd); >> +} >> + >> static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { >> .write_l = tegra_cqhci_writel, >> .enable = sdhci_tegra_cqe_enable, >> @@ -1366,6 +1395,7 @@ static const struct sdhci_ops tegra210_sdhci_ops = { >> .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, >> .voltage_switch = tegra_sdhci_voltage_switch, >> .get_max_clock = tegra_sdhci_get_max_clock, >> + .set_timeout = tegra_sdhci_set_timeout, >> }; >> >> static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { >> @@ -1403,6 +1433,7 @@ static const struct sdhci_ops tegra186_sdhci_ops = { >> .voltage_switch = tegra_sdhci_voltage_switch, >> .get_max_clock = tegra_sdhci_get_max_clock, >> .irq = sdhci_tegra_cqhci_irq, >> + .set_timeout = tegra_sdhci_set_timeout, >> }; >> >> static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { >> -- >> 2.7.4 >>