Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Marc Zyngier <maz@kernel.org>
To:     Thomas Gleixner <tglx@linutronix.de>
Cc:     Catalin Marinas <catalin.marinas@arm.com>,
        Mark Salter <msalter@redhat.com>,
        Robert Richter <rrichter@marvell.com>,
        Tim Harvey <tharvey@gateworks.com>,
        Jason Cooper <jason@lakedaemon.net>,
        linux-kernel@vger.kernel.org
Subject: [GIT PULL] irqchip fixes for 5.6, take #2
Date:   Sat, 14 Mar 2020 10:30:00 +0000
Message-Id: <20200314103000.2413-1-maz@kernel.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Hi Thomas,

This is hopefully the last irqchip update for 5.6. This time, a single
patch working around a hardware issue on the Cavium ThunderX and its
derivatives.

Please pull.

	M.

The following changes since commit 5186a6cc3ef5a3fa327c258924ef098b0de77006:

  irqchip/gic-v3-its: Rename VPENDBASER/VPROPBASER accessors (2020-02-08 10:01:33 +0000)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git tags/irqchip-fixes-5.6-2

for you to fetch changes up to d01fd161e85904064290435f67f4ed59af5daf74:

  irqchip/gic-v3: Workaround Cavium erratum 38539 when reading GICD_TYPER2 (2020-03-14 10:15:19 +0000)

----------------------------------------------------------------
irqchip fixes for 5.6, take #2

- Add workaround for Cavium/Marvell ThunderX unimplemented GIC registers

----------------------------------------------------------------
Marc Zyngier (1):
      irqchip/gic-v3: Workaround Cavium erratum 38539 when reading GICD_TYPER2

 Documentation/arm64/silicon-errata.rst |  2 ++
 drivers/irqchip/irq-gic-v3.c           | 30 +++++++++++++++++++++++++++++-
 2 files changed, 31 insertions(+), 1 deletion(-)