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Subject: Re: [RFC PATCH v4 8/8] arm64: tegra: Add Tegra VI CSI support in
 device tree
To:     Sowjanya Komatineni <skomatineni@nvidia.com>,
        thierry.reding@gmail.com, jonathanh@nvidia.com, frankc@nvidia.com,
        hverkuil@xs4all.nl, helen.koike@collabora.com, sboyd@kernel.org
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        linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <1584236766-24819-1-git-send-email-skomatineni@nvidia.com>
 <1584236766-24819-9-git-send-email-skomatineni@nvidia.com>
From:   Dmitry Osipenko <digetx@gmail.com>
Message-ID: <b4bbcc1d-d38c-14c5-7205-2f7657ab8712@gmail.com>
Date:   Sun, 15 Mar 2020 15:54:01 +0300
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15.03.2020 04:46, Sowjanya Komatineni пишет:
> Tegra210 contains VI controller for video input capture from MIPI
> CSI camera sensors and also supports built-in test pattern generator.
> 
> CSI ports can be one-to-one mapped to VI channels for capturing from
> an external sensor or from built-in test pattern generator.
> 
> This patch adds support for VI and CSI and enables them in Tegra210
> device tree.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---

Hello Sowjanya,

...
> +
> +			pd_venc: venc {
> +				clocks = <&tegra_car TEGRA210_CLK_VI>,
> +					 <&tegra_car TEGRA210_CLK_CSI>;
> +				resets = <&tegra_car 20>,

What is the clock #20?

> +					 <&tegra_car TEGRA210_CLK_CSI>,
> +					 <&mc TEGRA210_MC_RESET_VI>;

Does this order means that memory controller will be reset *after*
resetting the CSI/VI hardware? This is incorrect reset sequence.

The memory controller reset should be kept asserted during of the time
of the hardware resetting procedure.

The correct sequence should be as follows:

1. Assert MC
2. Reset VI
3. Deassert MC