Received: by 2002:a25:e7d8:0:0:0:0:0 with SMTP id e207csp2478686ybh; Mon, 16 Mar 2020 04:06:31 -0700 (PDT) X-Google-Smtp-Source: ADFU+vuJKUX3Wng+eIkGcck1CobTPOSXjOwduXgia6G+UIrXmKq6tDPaGBcCtZ3dk/Ng9NTOvEKC X-Received: by 2002:a05:6830:4ab:: with SMTP id l11mr1602657otd.163.1584356791352; Mon, 16 Mar 2020 04:06:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1584356791; cv=none; d=google.com; s=arc-20160816; b=EcmNRTFMAOYkFiuTxVF9QWjGiVc1JROzE72aRNpukoGtYUEAhWEiQ13F1HeE2Bibzs rqllh98BneLlmzPi1SYymkL9SIexRT7WcMhYLumUkKbTayux2OXZdhy+Rabn7GdZ/HHX fuewKQFlZbLwLxiMZHVi6pM4oNZ2+vwtPErfkxcM2lvhk6X23MtHm4Ihie0RZ50VACJW iJmgflSXe8LICMTqIhka15LkpcreqpozO3N7yK6RMw7uEb1eru8YTMXYXEqkH20CyYdV lALnQGI1FQm9ck0XoTWb7tb6qivVVWF/cGc6gCnPcDeLM9ugH9Dj952+kgD3W/EA4fCG zW/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=IdgQ5DKZEhk5bXvDveTDUIKKO9yLdxP1MVqiGBL6TkQ=; b=MbchiFgR4XmfFiUER6iaKBqYPTDl9HmOPY4Fj8mfLGa4O/dvYRGcMD6kgW8/WtnsYP avOxq8DlwlLISLoPYrMBSMMsCgwt0sLkntJa0FP02sFNy/a1wUtiLtLDcRTGlmI0IQW6 GptEFGDqr//Yl6OE7r2Yj5PsxPUFMPGglkCBgwWt7zUFl4wyzwOvhxhFmP/QRG8YL+lt 3rh7Kgg03WD0dyHUHa5gg9sYNo9iqMTQjxNaIZbeFBkvJTgB41S0DYRU6p2HUI7DYWyZ RGACBfh/6dUUvwEjmz8UD14HeuBF+5KvsSrxBoDi/B/Bvs8zBSSZ22Qcxef2O6ZbRIhv 6K/A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g13si513240otg.49.2020.03.16.04.06.18; Mon, 16 Mar 2020 04:06:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730764AbgCPLEf (ORCPT + 99 others); Mon, 16 Mar 2020 07:04:35 -0400 Received: from alexa-out-blr-01.qualcomm.com ([103.229.18.197]:27575 "EHLO alexa-out-blr-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730678AbgCPLEe (ORCPT ); Mon, 16 Mar 2020 07:04:34 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-01.qualcomm.com with ESMTP/TLS/AES256-SHA; 16 Mar 2020 16:33:03 +0530 Received: from mkrishn-linux.qualcomm.com ([10.204.66.35]) by ironmsg01-blr.qualcomm.com with ESMTP; 16 Mar 2020 16:32:44 +0530 Received: by mkrishn-linux.qualcomm.com (Postfix, from userid 438394) id E451444DD; Mon, 16 Mar 2020 16:32:43 +0530 (IST) From: Krishna Manikandan To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Krishna Manikandan , linux-kernel@vger.kernel.org, robdclark@gmail.com, seanpaul@chromium.org, hoegsberg@chromium.org, kalyan_t@codeaurora.org, nganji@codeaurora.org Subject: [v2] arm64: dts: sc7180: modify assigned clocks for sc7180 target Date: Mon, 16 Mar 2020 16:32:42 +0530 Message-Id: <1584356562-13181-1-git-send-email-mkrishn@codeaurora.org> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DISP_CC_MDSS_ROT_CLK and DISP_CC_MDSS_AHB_CLK in the assigned clocks list for sc7180 target. Signed-off-by: Krishna Manikandan --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 998f101..e3b60f1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1544,8 +1544,12 @@ clock-names = "iface", "rot", "lut", "core", "vsync"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; assigned-clock-rates = <300000000>, + <19200000>, + <19200000>, <19200000>; interrupt-parent = <&mdss>; -- 1.9.1