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[217.229.28.220]) by smtp.gmail.com with ESMTPSA id b187sm8795993wmc.14.2020.03.20.08.10.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 08:10:36 -0700 (PDT) Date: Fri, 20 Mar 2020 16:10:35 +0100 From: Thierry Reding To: Jon Hunter Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] soc/tegra: fuse: Add custom SoC attributes Message-ID: <20200320151035.GB3706404@ulmo> References: <20200320113716.6105-1-jonathanh@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="E39vaYmALEf/7YXx" Content-Disposition: inline In-Reply-To: <20200320113716.6105-1-jonathanh@nvidia.com> User-Agent: Mutt/1.13.1 (2019-12-14) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --E39vaYmALEf/7YXx Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Mar 20, 2020 at 11:37:16AM +0000, Jon Hunter wrote: > Add a custom SoC attribute for Tegra to expose the HIDREV register > contents to userspace via the sysfs. This register provides additional > details about the fabrication and versioning of the device. Exposing > this information is useful for identifying the exact device revision and > device type. >=20 > Please note that the fields in this register vary depending on the Tegra > generation and so instead of exposing the individual fields, just expose > the entire contents of the register. Details of the register fields can > be found in the Technical Reference Manual for each Tegra device. That seems a little suboptimal to me. It's pretty trivial for the kernel to distinguish between different SoC generations in order to know what the fields are. It's a lot more difficult for userspace to do so. Is the register completely different between SoC generations or just slightly? Having individual fields exposed as individual attributes seems like it would make it a lot easier for userspace to get at the needed bits. Thierry >=20 > Signed-off-by: Jon Hunter > --- > drivers/soc/tegra/fuse/fuse-tegra.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) >=20 > diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse= /fuse-tegra.c > index 802717b9f6a3..217e326da232 100644 > --- a/drivers/soc/tegra/fuse/fuse-tegra.c > +++ b/drivers/soc/tegra/fuse/fuse-tegra.c > @@ -300,6 +300,24 @@ static void tegra_enable_fuse_clk(void __iomem *base) > writel(reg, base + 0x14); > } > =20 > +static ssize_t tegra_soc_hidrev_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + return sprintf(buf, "%d\n", tegra_read_chipid()); Would it be better to print this as hexadecimal? > +} > + > +static DEVICE_ATTR(hidrev, S_IRUGO, tegra_soc_hidrev_show, NULL); > + > +static struct attribute *tegra_soc_attr[] =3D { > + &dev_attr_hidrev.attr, > + NULL, > +}; > + > +static const struct attribute_group tegra_soc_attr_group =3D { > + .attrs =3D tegra_soc_attr, > +}; > + > struct device * __init tegra_soc_device_register(void) > { > struct soc_device_attribute *attr; > @@ -312,6 +330,7 @@ struct device * __init tegra_soc_device_register(void) > attr->family =3D kasprintf(GFP_KERNEL, "Tegra"); > attr->revision =3D kasprintf(GFP_KERNEL, "%d", tegra_sku_info.revision); > attr->soc_id =3D kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); I guess we print all of these as decimal, so hidrev should probably be the same, so never mind the previous comment. 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