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From:   Eric Auger <eric.auger@redhat.com>
To:     eric.auger.pro@gmail.com, eric.auger@redhat.com,
        iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
        kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, joro@8bytes.org,
        alex.williamson@redhat.com, jacob.jun.pan@linux.intel.com,
        yi.l.liu@intel.com, jean-philippe.brucker@arm.com,
        will.deacon@arm.com, robin.murphy@arm.com
Cc:     marc.zyngier@arm.com, peter.maydell@linaro.org,
        zhangfei.gao@gmail.com
Subject: [PATCH v10 07/13] iommu/smmuv3: Allow stage 1 invalidation with unmanaged ASIDs
Date:   Fri, 20 Mar 2020 17:09:26 +0100
Message-Id: <20200320160932.27222-8-eric.auger@redhat.com>
In-Reply-To: <20200320160932.27222-1-eric.auger@redhat.com>
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With nested stage support, soon we will need to invalidate
S1 contexts and ranges tagged with an unmanaged asid, this
latter being managed by the guest. So let's introduce 2 helpers
that allow to invalidate with externally managed ASIDs

Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
 drivers/iommu/arm-smmu-v3.c | 36 ++++++++++++++++++++++++++++++------
 1 file changed, 30 insertions(+), 6 deletions(-)

diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 92a1a5ac5b50..39deddea6ae5 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -2301,13 +2301,18 @@ static int arm_smmu_atc_inv_domain(struct arm_smm=
u_domain *smmu_domain,
 }
=20
 /* IO_PGTABLE API */
-static void arm_smmu_tlb_inv_context(void *cookie)
+
+static void __arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_doma=
in,
+				       int ext_asid)
 {
-	struct arm_smmu_domain *smmu_domain =3D cookie;
 	struct arm_smmu_device *smmu =3D smmu_domain->smmu;
 	struct arm_smmu_cmdq_ent cmd;
=20
-	if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) {
+	if (ext_asid >=3D 0) { /* guest stage 1 invalidation */
+		cmd.opcode	=3D CMDQ_OP_TLBI_NH_ASID;
+		cmd.tlbi.asid	=3D ext_asid;
+		cmd.tlbi.vmid	=3D smmu_domain->s2_cfg->vmid;
+	} else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) {
 		cmd.opcode	=3D CMDQ_OP_TLBI_NH_ASID;
 		cmd.tlbi.asid	=3D smmu_domain->s1_cfg->cd.asid;
 		cmd.tlbi.vmid	=3D 0;
@@ -2328,9 +2333,17 @@ static void arm_smmu_tlb_inv_context(void *cookie)
 	arm_smmu_atc_inv_domain(smmu_domain, 0, 0, 0);
 }
=20
-static void arm_smmu_tlb_inv_range(unsigned long iova, size_t size,
+static void arm_smmu_tlb_inv_context(void *cookie)
+{
+	struct arm_smmu_domain *smmu_domain =3D cookie;
+
+	__arm_smmu_tlb_inv_context(smmu_domain, -1);
+}
+
+static void __arm_smmu_tlb_inv_range(unsigned long iova, size_t size,
 				   size_t granule, bool leaf,
-				   struct arm_smmu_domain *smmu_domain)
+				   struct arm_smmu_domain *smmu_domain,
+				   int ext_asid)
 {
 	struct arm_smmu_device *smmu =3D smmu_domain->smmu;
 	unsigned long start =3D iova, end =3D iova + size, num_pages =3D 0, tg =
=3D 0;
@@ -2345,7 +2358,11 @@ static void arm_smmu_tlb_inv_range(unsigned long i=
ova, size_t size,
 	if (!size)
 		return;
=20
-	if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) {
+	if (ext_asid >=3D 0) {  /* guest stage 1 invalidation */
+		cmd.opcode	=3D CMDQ_OP_TLBI_NH_VA;
+		cmd.tlbi.asid	=3D ext_asid;
+		cmd.tlbi.vmid	=3D smmu_domain->s2_cfg->vmid;
+	} else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) {
 		cmd.opcode	=3D CMDQ_OP_TLBI_NH_VA;
 		cmd.tlbi.asid	=3D smmu_domain->s1_cfg->cd.asid;
 	} else {
@@ -2405,6 +2422,13 @@ static void arm_smmu_tlb_inv_range(unsigned long i=
ova, size_t size,
 	arm_smmu_atc_inv_domain(smmu_domain, 0, start, size);
 }
=20
+static void arm_smmu_tlb_inv_range(unsigned long iova, size_t size,
+				   size_t granule, bool leaf,
+				   struct arm_smmu_domain *smmu_domain)
+{
+	__arm_smmu_tlb_inv_range(iova, size, granule, leaf, smmu_domain, -1);
+}
+
 static void arm_smmu_tlb_inv_page_nosync(struct iommu_iotlb_gather *gath=
er,
 					 unsigned long iova, size_t granule,
 					 void *cookie)
--=20
2.20.1