Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D1F87C433D2
Subject: Re: [PATCH v2 1/2] clk: qcom: gcc: Add USB3 PIPE clock and GDSC for
 SM8150
To:     Stephen Boyd <sboyd@kernel.org>, agross@kernel.org,
        bjorn.andersson@linaro.org, mark.rutland@arm.com,
        mturquette@baylibre.com, robh+dt@kernel.org
Cc:     linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
References: <1584478412-7798-1-git-send-email-wcheng@codeaurora.org>
 <1584478412-7798-2-git-send-email-wcheng@codeaurora.org>
 <158474728076.125146.11401827374115414324@swboyd.mtv.corp.google.com>
From:   Wesley Cheng <wcheng@codeaurora.org>
Message-ID: <83787def-4ea5-d38d-d745-ea30a914a05f@codeaurora.org>
Date:   Fri, 20 Mar 2020 17:25:37 -0700
User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101
 Thunderbird/68.6.0
MIME-Version: 1.0
In-Reply-To: <158474728076.125146.11401827374115414324@swboyd.mtv.corp.google.com>
Content-Type: text/plain; charset=utf-8
Content-Language: en-US
Content-Transfer-Encoding: 7bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk


On 3/20/2020 4:34 PM, Stephen Boyd wrote:
> Quoting Wesley Cheng (2020-03-17 13:53:31)
>> diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
>> index 90d60ef..3e1a918 100644
>> --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h
>> +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
>> @@ -240,4 +240,8 @@
>>  #define GCC_USB30_SEC_BCR                                      27
>>  #define GCC_USB_PHY_CFG_AHB2PHY_BCR                            28
>>  
>> +/* GCC GDSCRs */
>> +#define USB30_PRIM_GDSC                     4
>> +#define USB30_SEC_GDSC                                         5
> 
> BTW, should we expect more GDSCs at 0,1,2,3 here? Why wasn't that done
> initially?
> 

Hi Stephen,

Yes, I assume there should be more GDSCs being introduced, and I have
notified Taniya (our GCC POC) to upload the rest of the GDSC changes.  I
decided to keep it with values 4 and 5 in order to be consistent with
previous chipsets, but if you feel we should shuffle these values, then
I am OK with that as well.

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project