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From:   "Voon, Weifeng" <weifeng.voon@intel.com>
To:     Jose Abreu <Jose.Abreu@synopsys.com>,
        "David S . Miller" <davem@davemloft.net>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>
CC:     "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Giuseppe Cavallaro" <peppe.cavallaro@st.com>,
        Andrew Lunn <andrew@lunn.ch>,
        Alexandre Torgue <alexandre.torgue@st.com>,
        "Ong, Boon Leong" <boon.leong.ong@intel.com>
Subject: RE: [RFC,net-next,v1, 1/1] net: stmmac: Enable SERDES power up/down
 sequence
Thread-Topic: [RFC,net-next,v1, 1/1] net: stmmac: Enable SERDES power up/down
 sequence
Thread-Index: AQHWAE0vpBWvWDPaGkGozDEPMDm2A6hVzcSAgAAFr0CAAAz8AIAAbqEw
Date:   Mon, 23 Mar 2020 15:52:13 +0000
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References: <20200322132342.2687-1-weifeng.voon@intel.com>
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> > > > This patch is to enable Intel SERDES power up/down sequence. The
> > > > SERDES converts 8/10 bits data to SGMII signal. Below is an
> > > > example of HW configuration for SGMII mode. The SERDES is located
> > > > in the PHY IF in the diagram below.
> > > >
> > > > <-----------------GBE Controller---------->|<--External PHY
> > > > chip-->
> > > > +----------+         +----+            +---+           +----------
> +
> > > > |   EQoS   | <-GMII->| DW | < ------ > |PHY| <-SGMII-> | External
> |
> > > > |   MAC    |         |xPCS|            |IF |           | PHY
> |
> > > > +----------+         +----+            +---+           +----------
> +
> > > >        ^               ^                 ^                ^
> > > >        |               |                 |                |
> > > >        +---------------------MDIO-------------------------+
> > > >
> > > > PHY IF configuration and status registers are accessible through
> > > > mdio address 0x15 which is defined as intel_adhoc_addr. During D0,
> > > > The driver will need to power up PHY IF by changing the power
> state to P0.
> > > > Likewise, for D3, the driver sets PHY IF power state to P3.
> > >
> > > I don't think this is the right approach.
> > >
> > > You could just add a new "mdio-intel-serdes" to phy/ folder just
> > > like I did with XPCS because this is mostly related with PHY
> > > settings rather than EQoS.
> > I am taking this approach to put it in stmmac folder rather than phy
> > folder as a generic mdio-intel-serdes as this is a specific Intel
> > serdes architecture which would only pair with DW EQos and DW xPCS HW.
> > Since this serdes will not able to pair other MAC or other non-Intel
> > platform, I would like you to reconsider this approach. I am open for
> discussion.
> > Thanks Jose for the fast response.
>=20
> OK, then I think we should use the BSP init/exit functions that are
> already available for platform setups (.init and .exit callback of
> plat_stmmacenet_data struct). We just need to extend this to PCI based
> setups.
>=20
> You can take a look at stmmac_platform.c and check what's done.
> Basically:
> 	- Call priv->plat->init() at probe() and resume()
> 	- Call priv->plat->exit() at remove() and suspend()
>=20
I have 2 concern if using the suggested BSP init/exit function.
1. Serdes is configured through MDIO bus. But the mdio bus register only ha=
ppens
in stmmac_dvr_probe() in stmmac_main.c.=20

2. All tx/rx packets requires serdes to be in the correct power state. If t=
he driver=20
power-down before stopping all the dma, it will cause tx queue timeout as p=
ackets=20
are not able to be transmitted out. Hence, the serdes cannot be power-down =
before calling
the stmmac_dvr_remove(). The stmmac_dvr_remove() will unregister the mdio b=
us. So, the=20
driver cannot powerdown the serdes after the stmmac_dvr_remove() too.   =20

Regards,
Weifeng

> ---
> Thanks,
> Jose Miguel Abreu