Received: by 2002:a25:6193:0:0:0:0:0 with SMTP id v141csp3963040ybb; Mon, 23 Mar 2020 10:55:31 -0700 (PDT) X-Google-Smtp-Source: ADFU+vtnrkanTS6TU75BPCaWien3hw/zn98fpc9DJWX5c7cJXd4yWqr4YZ1hJdEz5NgR9Eb/SBrk X-Received: by 2002:aca:3089:: with SMTP id w131mr387748oiw.121.1584986131827; Mon, 23 Mar 2020 10:55:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1584986131; cv=none; d=google.com; s=arc-20160816; b=UZf0We+gmq38Ok/aMlSF0GVRqGWAm+aDeHOsfJlJcr0nGb1pykQXknOeWLFrTdriqQ uGQXuUlhzquuG/Yg9xWBZSmd55uOnB1HcjPlrl3Ytx3omaUZ1VC6Tf1kg4Hak1vECIM3 mDhpXwJI8X50N2YaJIPbVDYPzST9Lb/pskZ0TiAFdDbHXjQSPxgBlKdGfw8akO32mzP9 8nUTw4DGDYfcjdpvjbgU+kWKW6OEnZNujAQmMcAaj7ao/E9iVDICJwYS7THAY1J0yRwB GcSjQrJbTacRYCvFcU8wtW6U+/URAkOab3uic9DxO19lnXTNCWSDAbZZFF6llpCaesu+ x3BA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=qg4/50YwdGiG0ifmC8NW2wUPpPGLSESHVND184P5UFw=; b=Pb/niRPkLixeEg0lklyJbQkbk2MN7XLTkvpd52foottFavvtKOAkl3UE5nSGRqF18u 99XGgWVbtyZgjqWssPgx/uKReV+9JkR2u+ABBfi0EOk3EiUEnEgo3vmGXM2g6qa+0Yt3 15aT2I5LrUS+PdSXBd83cPAa7nN3raCIDgVfk9gz3jkjJzx51BAZrrlfSaoJjOutXND/ NZP/8ga6KZhPRUaxN4TRhbC7kQDlbHTqkVEDpMKURZhTn6pQe6G1vqFvT7xIF7jWp1hp O0PG0yLR7SsUhGgTUs2K87303DdKeu5iAjGMluYH1BB369j3Jr1VhmLrodYJCnFlMNAu bEoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=kFzaIrtx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a15si7920600otj.205.2020.03.23.10.55.18; Mon, 23 Mar 2020 10:55:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=kFzaIrtx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727850AbgCWRwq (ORCPT + 99 others); Mon, 23 Mar 2020 13:52:46 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:17093 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727803AbgCWRwo (ORCPT ); Mon, 23 Mar 2020 13:52:44 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 23 Mar 2020 10:51:13 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 23 Mar 2020 10:52:43 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 23 Mar 2020 10:52:43 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Mar 2020 17:52:43 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 23 Mar 2020 17:52:42 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.78]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 23 Mar 2020 10:52:42 -0700 From: Sowjanya Komatineni To: , , , , , CC: , , , , , , Subject: [RFC PATCH v5 9/9] arm64: tegra: Add Tegra VI CSI support in device tree Date: Mon, 23 Mar 2020 10:52:35 -0700 Message-ID: <1584985955-19101-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> References: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584985873; bh=qg4/50YwdGiG0ifmC8NW2wUPpPGLSESHVND184P5UFw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=kFzaIrtxtdihQI5PAHWVWD/UqOIby7BGGDpM+ZaaV/ObTaFIMJs+ZJWEWARzbmnXT Ca204D+JfmYqEQNxS8Rh24W/uHV2S3AhvYPNR6ZQgEmZhYyLa4CH9oOu1+XLiiBtaF zZqG/v/6VGz9uuAS1exEQMqWOkOKo6mDGJmhVvSLmcYvLnkh1fBPVH8J36Jmhn14Rg yzHqgp0rFSHyF6z5PcjxpQVFLNW1phlCBNXTIiRIe10ZnjaaGjO9zkHzbPS/kMwIrN 6UgbN+jg/cWGn+mTW9SyomtuhIZYwvL1Be1T1gKqRdQS8ktM0A26X4/z6O1tuD8Pv4 t0wEW0mA7D7Tg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra210 contains VI controller for video input capture from MIPI CSI camera sensors and also supports built-in test pattern generator. CSI ports can be one-to-one mapped to VI channels for capturing from an external sensor or from built-in test pattern generator. This patch adds support for VI and CSI and enables them in Tegra210 device tree. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 10 ++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 45 +++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 313a4c2..b57d837 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -14,6 +14,16 @@ status = "okay"; }; + vi@54080000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + + csi@838 { + status = "okay"; + }; + }; + sor@54580000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 5b1dfd8..2deba87 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -137,9 +137,43 @@ vi@54080000 { compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x00040000>; + reg = <0x0 0x54080000 0x0 0x700>; interrupts = ; status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + clock-names = "vi"; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>; + clock-names = "csi", "cilab", "cilcd", "cile"; + power-domains = <&pd_sor>; + }; + }; tsec@54100000 { @@ -839,6 +873,15 @@ reset-names = "vic"; #power-domain-cells = <0>; }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA210_CLK_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + resets = <&mc TEGRA210_MC_RESET_VI>, + <&tegra_car TEGRA210_RST_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + #power-domain-cells = <0>; + }; }; sdmmc1_3v3: sdmmc1-3v3 { -- 2.7.4