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[94.29.39.224]) by smtp.googlemail.com with ESMTPSA id a22sm3245335ljm.28.2020.03.24.12.20.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Mar 2020 12:20:02 -0700 (PDT) Subject: Re: [RFC PATCH v5 5/9] dt-binding: tegra: Add VI and CSI bindings To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, frankc@nvidia.com, hverkuil@xs4all.nl, helen.koike@collabora.com Cc: sboyd@kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> <1584985955-19101-6-git-send-email-skomatineni@nvidia.com> From: Dmitry Osipenko Message-ID: <2256dc66-f3f9-3400-85e9-0641729b1316@gmail.com> Date: Tue, 24 Mar 2020 22:20:01 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <1584985955-19101-6-git-send-email-skomatineni@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 23.03.2020 20:52, Sowjanya Komatineni пишет: > Tegra contains VI controller which can support up to 6 MIPI CSI > camera sensors. > > Each Tegra CSI port from CSI unit can be one-to-one mapper to > VI channel and can capture from an external camera sensor or > from built-in test pattern generator. > > This patch adds dt-bindings for Tegra VI and CSI. > > Signed-off-by: Sowjanya Komatineni > --- > .../display/tegra/nvidia,tegra20-host1x.txt | 67 +++++++++++++++++----- > 1 file changed, 54 insertions(+), 13 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > index 9999255..9421569 100644 > --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > @@ -40,14 +40,25 @@ of the following host1x client modules: > > Required properties: > - compatible: "nvidia,tegra-vi" > - - reg: Physical base address and length of the controller's registers. > + - reg: Physical base address and length of the controller registers. > - interrupts: The interrupt outputs from the controller. > - - clocks: Must contain one entry, for the module clock. > + - clocks: Must contain an entry for the module clock "vi" > See ../clocks/clock-bindings.txt for details. > - - resets: Must contain an entry for each entry in reset-names. > - See ../reset/reset.txt for details. > - - reset-names: Must include the following entries: > - - vi This should be a wrong change because ARM32 Tegra SoCs do not use power domain. > + - power-domains: Must include venc powergate node as vi is in VE partition.