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From:   Jiaxun Yang <jiaxun.yang@flygoat.com>
To:     linux-mips@vger.kernel.org
Cc:     Jiaxun Yang <jiaxun.yang@flygoat.com>,
        Huacai Chen <chenhc@lemote.com>, Marc Zyngier <maz@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
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Message-ID: <20200325022916.106641-4-jiaxun.yang@flygoat.com>
Subject: [PATCH v7 02/12] irqchip: loongson-liointc: Workaround LPC IRQ Errata
Date:   Wed, 25 Mar 2020 10:28:19 +0800
In-Reply-To: <20200325022916.106641-1-jiaxun.yang@flygoat.com>
References: <20200325022916.106641-1-jiaxun.yang@flygoat.com>
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The 1.0 version of that controller has a bug that status bit
of LPC IRQ sometimes doesn't get set correctly.

So we can always blame LPC IRQ when spurious interrupt happens
at the parent interrupt line which LPC IRQ supposed to route
to.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Co-developed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
---
 drivers/irqchip/irq-loongson-liointc.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-l=
oongson-liointc.c
index 18de2c09ece4..7d2339e638db 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -32,6 +32,8 @@
=20
 #define LIOINTC_SHIFT_INTx=094
=20
+#define LIOINTC_ERRATA_IRQ=0910
+
 struct liointc_handler_data {
 =09struct liointc_priv=09*priv;
 =09u32=09=09=09parent_int_map;
@@ -41,6 +43,7 @@ struct liointc_priv {
 =09struct irq_chip_generic=09=09*gc;
 =09struct liointc_handler_data=09handler[LIOINTC_NUM_PARENT];
 =09u8=09=09=09=09map_cache[LIOINTC_CHIP_IRQ];
+=09bool=09=09=09=09have_lpc_irq_errata;
 };
=20
 static void liointc_chained_handle_irq(struct irq_desc *desc)
@@ -54,8 +57,15 @@ static void liointc_chained_handle_irq(struct irq_desc *=
desc)
=20
 =09pending =3D readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
=20
-=09if (!pending)
-=09=09spurious_interrupt();
+=09if (!pending) {
+=09=09/* Always blame LPC IRQ if we have that bug */
+=09=09if (handler->priv->have_lpc_irq_errata &&
+=09=09=09(handler->parent_int_map & ~gc->mask_cache &
+=09=09=09BIT(LIOINTC_ERRATA_IRQ)))
+=09=09=09pending =3D BIT(LIOINTC_ERRATA_IRQ);
+=09=09else
+=09=09=09spurious_interrupt();
+=09}
=20
 =09while (pending) {
 =09=09int bit =3D __ffs(pending);
--=20
2.26.0.rc2