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Subject: Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET
 instructions
From:   Adrian Hunter <adrian.hunter@intel.com>
To:     Mingbo Zhang <whensungoes@gmail.com>, x86@kernel.org
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        "H. Peter Anvin" <hpa@zytor.com>,
        Masami Hiramatsu <mhiramat@kernel.org>,
        Arnaldo Carvalho de Melo <acme@redhat.com>,
        Andi Kleen <ak@linux.intel.com>,
        Josh Poimboeuf <jpoimboe@redhat.com>,
        linux-kernel@vger.kernel.org, Yu-cheng Yu <yu-cheng.yu@intel.com>,
        Jiri Olsa <jolsa@redhat.com>
References: <20200303045033.6137-1-whensungoes@gmail.com>
 <931d8779-8b77-b75f-bb3a-ee2f9d75f149@intel.com>
 <a384009b-0b5d-22da-5613-870c85c546df@intel.com>
Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki,
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Message-ID: <06eec783-733c-c8e1-441b-2d25b897485c@intel.com>
Date:   Wed, 25 Mar 2020 08:10:36 +0200
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On 16/03/20 9:10 am, Adrian Hunter wrote:
> On 3/03/20 9:17 am, Adrian Hunter wrote:
>> On 3/03/20 6:50 am, Mingbo Zhang wrote:
>>> Intel CET instructions are not described in the Intel SDM. When trying to
>>> get the instruction length, the following instructions get wrong (missing
>>> ModR/M byte).
>>>
>>> RDSSPD r32
>>> RSDDPQ r64
>>> ENDBR32
>>> ENDBR64
>>> WRSSD r/m32, r32
>>> WRSSQ r/m64, r64
>>>
>>> RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which is
>>> described in SDM as Reserved-NOP with no encoding characters, and got an
>>> empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got an empty slot.
>>
>> We have patches for that:
>>
>> 	https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel.com/
>>
>> But they have not yet been applied.  Arnaldo, could you take them?
>>
> 
> Any takers?
> 

:-)