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Subject: Re: [RFC PATCH v5 6/9] media: tegra: Add Tegra210 Video input driver
To:     Sowjanya Komatineni <skomatineni@nvidia.com>,
        thierry.reding@gmail.com, jonathanh@nvidia.com, frankc@nvidia.com,
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From:   Dmitry Osipenko <digetx@gmail.com>
Message-ID: <265b13e7-633f-5fa4-8df9-e461bf7e386a@gmail.com>
Date:   Wed, 25 Mar 2020 22:43:22 +0300
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25.03.2020 04:15, Sowjanya Komatineni пишет:
> 
> On 3/24/20 6:08 PM, Sowjanya Komatineni wrote:
>>
>> On 3/24/20 5:34 PM, Dmitry Osipenko wrote:
>>> External email: Use caution opening links or attachments
>>>
>>>
>>> 23.03.2020 20:52, Sowjanya Komatineni пишет:
>>>> +static void tegra_channel_vi_soft_reset(struct tegra_vi_channel *chan)
>>>> +{
>>>> +     /* disable clock gating to enable continuous clock */
>>>> +     tegra_vi_write(chan, TEGRA_VI_CFG_CG_CTRL, 0);
>>>> +     /*
>>>> +      * Soft reset memory client interface, pixel format logic, sensor
>>>> +      * control logic, and a shadow copy logic to bring VI to clean
>>>> state.
>>>> +      */
>>>> +     vi_csi_write(chan, TEGRA_VI_CSI_SW_RESET, 0xf);
>>>> +     usleep_range(100, 200);
>>>> +     vi_csi_write(chan, TEGRA_VI_CSI_SW_RESET, 0x0);
>>> Is it safe to reset MCCIF without blocking and flushing memory requests
>>> at first?
>> Yes to bring VI to clean state on errors its recommended by HW design
>> team.
> BTW, just to be clear this is Software reset.

Ok