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Lu" To: Richard Cochran CC: "linux-kernel@vger.kernel.org" , "netdev@vger.kernel.org" , "David S . Miller" , Vladimir Oltean , Claudiu Manoil , Andrew Lunn , Vivien Didelot , Florian Fainelli , Alexandre Belloni , Microchip Linux Driver Support Subject: RE: [PATCH 6/6] ptp_ocelot: support 4 programmable pins Thread-Topic: [PATCH 6/6] ptp_ocelot: support 4 programmable pins Thread-Index: AQHV/qQWBIiKj5A/T0WD8BjMeGVxRqhXvRSAgADnAvCAALTjgIABSqMQ Date: Thu, 26 Mar 2020 09:34:52 +0000 Message-ID: References: <20200320103726.32559-1-yangbo.lu@nxp.com> <20200320103726.32559-7-yangbo.lu@nxp.com> <20200324130733.GA18149@localhost> <20200325134147.GB32284@localhost> In-Reply-To: <20200325134147.GB32284@localhost> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yangbo.lu@nxp.com; x-originating-ip: [92.121.36.198] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 0f903f43-6b07-4c06-472c-08d7d168f007 x-ms-traffictypediagnostic: AM7PR04MB7080:|AM7PR04MB7080: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1388; x-forefront-prvs: 0354B4BED2 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(346002)(136003)(39860400002)(366004)(376002)(396003)(86362001)(7696005)(4326008)(5660300002)(2906002)(55016002)(6916009)(33656002)(52536014)(6506007)(9686003)(53546011)(76116006)(66946007)(316002)(54906003)(26005)(186003)(66556008)(66476007)(66446008)(64756008)(8936002)(478600001)(81156014)(8676002)(81166006)(71200400001);DIR:OUT;SFP:1101;SCL:1;SRVR:AM7PR04MB7080;H:AM7PR04MB6885.eurprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: s3ywO7V+li3Cj1tIhojGN6GKpe4EfIUvz68AaHSpUYzgjCKsJqVlu5JJKWwPt3Ne7wiQJ8XsDgJu5aCizmwqbKOOxpxOQc6vL0kVvAKrN54Zf82Aa5ZH2z+rqnWMRcuV3XLZ2Oy7J4axyfLWx9xyr50oXuHmE6C+2lrezzlBRLQYwHlmqfj2GuQd5kyziQHICSR9+VOxnxDLoseEORdjFq/VZ0YsQxpEgiVuv9LZg0XXP8mRt3OpuqNV5SrJltyfLvIwjH8S+BtYL7udV0u/+7msVKN55uo5ANcPtnp0xKDmzu4xz0DiV6hd8IwyNlcq6cSx8Wbf7vf3pJdPSsNMEwveToqmYgjR4voG27G6wL9cu3CD7W6hR+VsxLJhhnjx4XHIWF9Q58/YLGnF53LoSAt4JZL+zajyXCN4N3A+dsRdt+cLLjrdMZy0AE1Ua5+R x-ms-exchange-antispam-messagedata: 89RjFlzbDZH7abbyKdQFW6r/B9PSLxWdI7SH2Lv4lokG7xSEXegu8YGsB46x4PyOyrvd8TrL4EEV+HWk1y3ws61tzeiy8OTNYb2sBr5xw4/MToT6xK1ZxhTTUcj1tii42x7NeHKMubM2HNDna9ks1Q== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0f903f43-6b07-4c06-472c-08d7d168f007 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Mar 2020 09:34:52.8952 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: wQULQH6Ae/O2dU4ZRojuuFi4VV8U9OCN3ILoM+TxCtHti7HDY0hLlc/3e6gpdi1Ewjnx8g+4t3ncxZhgkKSiNg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR04MB7080 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Richard, > -----Original Message----- > From: Richard Cochran > Sent: Wednesday, March 25, 2020 9:42 PM > To: Y.b. Lu > Cc: linux-kernel@vger.kernel.org; netdev@vger.kernel.org; David S . Mille= r > ; Vladimir Oltean ; > Claudiu Manoil ; Andrew Lunn ; > Vivien Didelot ; Florian Fainelli > ; Alexandre Belloni = ; > Microchip Linux Driver Support > Subject: Re: [PATCH 6/6] ptp_ocelot: support 4 programmable pins >=20 > On Wed, Mar 25, 2020 at 03:08:46AM +0000, Y.b. Lu wrote: >=20 > > The calling should be like this, > > ptp_set_pinfunc (hold pincfg_mux) > > ---> ptp_disable_pinfunc > > ---> .enable > > ---> ptp_find_pin (hold pincfg_mux) >=20 > I see. The call >=20 > ptp_disable_pinfunc() --> .enable() >=20 > is really >=20 > ptp_disable_pinfunc() --> .enable(on=3D0) >=20 > or disable. >=20 > All of the other drivers (except mv88e6xxx which has a bug) avoid the > deadlock by only calling ptp_find_pin() when invoked by .enable(on=3D1); >=20 > Of course, that is horrible, and I am going to find a way to fix it. Thanks a lot. Do you think it is ok to move protection into ptp_set_pinfunc() to protect = just pin_config accessing? ptp_disable_pinfunc() not touching pin_config could be out of protection. But it seems indeed total ptp_set_pinfunc() should be under protection... >=20 > For now, maybe you can drop the "programmable pins" feature for your > driver? After all, the pins are not programmable. I still want to confirm, did you mean the deadlock issue? Or you thought th= e pin supports only PTP_PF_PEROUT in hardware? I could modify commit messages to indicate the pin supports both PTP_PF_PER= OUT and PTP_PF_EXTTS, and PTP_PF_EXTTS support will be added in the future. Thanks a lot. >=20 > Thanks, > Richard