Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Date:   Thu, 26 Mar 2020 17:43:05 +0100
From:   Oscar Carter <oscar.carter@gmx.com>
To:     Dan Carpenter <dan.carpenter@oracle.com>
Cc:     Oscar Carter <oscar.carter@gmx.com>,
        Forest Bond <forest@alittletooquiet.net>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        devel@driverdev.osuosl.org, Malcolm Priestley <tvboxspy@gmail.com>,
        Mukesh Ojha <mojha@codeaurora.org>,
        linux-kernel@vger.kernel.org,
        Ojaswin Mujoo <ojaswin25111998@gmail.com>
Subject: Re: [PATCH] staging: vt6656: Use BIT() macro instead of hex value
Message-ID: <20200326164304.GA3629@ubuntu>
References: <20200320171056.7841-1-oscar.carter@gmx.com>
 <20200323073518.GK4650@kadam>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20200323073518.GK4650@kadam>
User-Agent: Mutt/1.10.1 (2018-07-13)
Content-Transfer-Encoding: quoted-printable
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Mon, Mar 23, 2020 at 10:35:18AM +0300, Dan Carpenter wrote:
> On Fri, Mar 20, 2020 at 06:10:56PM +0100, Oscar Carter wrote:
> > -#define RSR_ADDRBROAD       0x80
> > -#define RSR_ADDRMULTI       0x40
> > +#define RSR_ADDRBROAD       BIT(7)
> > +#define RSR_ADDRMULTI       BIT(6)
> >  #define RSR_ADDRUNI         0x00
> > -#define RSR_IVLDTYP         0x20        /* invalid packet type */
> > -#define RSR_IVLDLEN         0x10        /* invalid len (> 2312 byte) =
*/
> > -#define RSR_BSSIDOK         0x08
> > -#define RSR_CRCOK           0x04
> > -#define RSR_BCNSSIDOK       0x02
> > -#define RSR_ADDROK          0x01
> > +#define RSR_IVLDTYP         BIT(5)	/* invalid packet type */
> > +#define RSR_IVLDLEN         BIT(4)	/* invalid len (> 2312 byte) */
> > +#define RSR_BSSIDOK         BIT(3)
> > +#define RSR_CRCOK           BIT(2)
> > +#define RSR_BCNSSIDOK       BIT(1)
> > +#define RSR_ADDROK          BIT(0)
>
> I like these ones because I do think the new version is more clear
> now.
>
> >  /* Bits in the EnhanceCFG_0 register */
> >  #define EnCFG_BBType_a		0x00
> > -#define EnCFG_BBType_b		0x01
> > -#define EnCFG_BBType_g		0x02
> > -#define EnCFG_BBType_MASK	0x03
> > -#define EnCFG_ProtectMd		0x20
> > +#define EnCFG_BBType_b		BIT(0)
> > +#define EnCFG_BBType_g		BIT(1)
> > +#define EnCFG_BBType_MASK	(BIT(0) | BIT(1))
> > +#define EnCFG_ProtectMd		BIT(5)
>
> Probably EnCFG_BBType_MASK should be defined using the other defines.
>
> #define EnCFG_BBType_MASK (EnCFG_BBType_b | EnCFG_BBType_g)
>
> Otherwise it looks good.  Can you change that one thing and then add
> my Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com>
>
Ok, i will make this change and i will send and incremental patch with the
"Fixes:" tag due to the this patch has already been added to the staging-n=
ext
branch of the greg staging tree.

> regards,
> dan carpenter
>
thanks,

oscar carter